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2003.10.15
S3C2440X RISC MICROPROCESSOR
PRODUCT OVERVIEW
PRODUCT OVERVIEW
INTRODUCTION
This manual describes SAMSUNG's S3C2440X 16/32-bit RISC microprocessor. SAMSUNG's S3C24440X is designed to provide hand-held devices and general applications with low-power, and high-performance microcontroller solution in small die size. To reduce total system cost, the S3C2440X includes the following components separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD Controller (STN & TFT), NAND Flash Boot Loader, System Manager (chip select logic and SDRAM Controller), 3-ch UART, 4-ch DMA, 4-ch Timers with PWM, I/O Ports, RTC, 8-ch 10-bit ADC and Touch Screen Interface, Camera interface, IIC-BUS Interface, IIS-BUS Interface, USB Host, USB Device, SD Host & Multi-Media Card Interface, 2ch SPI and PLL for clock generation. The S3C2440X has been developed using an ARM920T core, 0.13um CMOS standard cells and a memory complier. Its low-power, simple, elegant and fully static design is particularly suitable for cost- and power-sensitive applications. It adopts a new bus architecture known as Advanced Micro controller Bus Architecture (AMBA). The S3C2440X offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed by Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with an 8-word line length. By providing a complete set of common system peripherals, the S3C2440X minimizes overall system costs and eliminates the need to configure additional components. The integrated on-chip functions that are described in this document include:
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1.2V internal, 1.8V/2.5V/3.3V memory, 3.3V external I/O microprocessor with 16KB I-Cache/16KB DCache/MMU External memory controller (SDRAM Control and Chip Select logic) LCD controller (up to 4K color STN and 256K color TFT) with 1-ch LCD-dedicated DMA 4-ch DMAs with external request pins 3-ch UART (IrDA1.0, 64-Byte Tx FIFO, and 64-Byte Rx FIFO) / 2-ch SPI 1-ch multi-master IIC-BUS/1-ch IIS-BUS controller SD Host interface version 1.0 & Multi-Media Card Protocol version 2.11 compatible 2-port USB Host /1- port USB Device (ver 1.1) 4-ch PWM timers & 1-ch internal timer Watch Dog Timer 130-bit general purpose I/O ports / 24-ch external interrupt source Power control: Normal, Slow, Idle and Sleep mode 8-ch 10-bit ADC and Touch screen interface RTC with calendar function On-chip clock generator with PLL
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
PRODUCT OVERVIEW
S3C2440X
FEATURES
Architecture
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NAND Flash Boot Loader
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Integrated system for hand-held devices and general embedded applications. 16/32-Bit RISC architecture and powerful instruction set with ARM920T CPU core. Enhanced ARM architecture MMU to support WinCE, EPOC 32 and Linux. Instruction cache, data cache, write buffer and Physical address TAG RAM to reduce the effect of main memory bandwidth and latency on performance. ARM920T CPU core supports the ARM debug architecture. Internal Advanced Microcontroller Bus Architecture (AMBA) (AMBA2.0, AHB/APB).
Supports booting from NAND flash memory. 4KB internal buffer for booting. Supports storage memory for NAND flash memory after booting. Supports Advanced NAND flash
Cache Memory
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64-way set-associative cache with I-Cache (16KB) and D-Cache (16KB). 8words length per line with one valid bit and two dirty bits per line. Pseudo random or round robin replacement algorithm. Write-through or write-back cache operation to update the main memory. The write buffer can hold 16 words of data and four addresses.
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System Manager
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Little/Big Endian support. Address space: 128M bytes for each bank (total 1G bytes). Supports programmable 8/16/32-bit data bus width for each bank. Fixed bank start address from bank 0 to bank 6. Programmable bank start address and bank size for bank 7. Eight memory banks: - Six memory banks for ROM, SRAM, and others. - Two memory banks for ROM/SRAM/ Synchronous DRAM.
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Clock & Power Manager
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On-chip MPLL and UPLL: UPLL generates the clock to operate USB Host/Device. MPLL generates the clock to operate MCU at maximum 400Mhz @ 1.2V. Clock can be fed selectively to each function block by software. Power mode: Normal, Slow, Idle, and Sleep mode Normal mode: Normal operating mode Slow mode: Low frequency clock without PLL Idle mode: The clock for only CPU is stopped. Sleep mode: The Core power including all peripherals is shut down. Woken up by EINT[15:0] or RTC alarm interrupt from Sleep mode
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Complete Programmable access cycles for all memory banks. Supports external wait signals to expend the bus cycle. Supports self-refresh mode in SDRAM for powerdown. Supports various types of ROM for booting (NOR/NAND Flash, EEPROM, and others).
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
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S3C2440X
PRODUCT OVERVIEW
FEATURES (Continued)
Interrupt Controller
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64-byte Rx FIFO. DMA Controller
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59 Interrupt sources (One Watch dog timer, 5 timers, 9 UARTs, 24 external interrupts, 4 DMA, 2 RTC, 2 ADC, 1 IIC, 2 SPI, 1 SDI, 2 USB, 1 LCD, 1 Battery Fault, 1 NAND and 2 Camera) Level/Edge mode on external interrupt source Programmable polarity of edge and level Supports Fast Interrupt request (FIQ) for very urgent interrupt request
4-ch DMA controller Supports memory to memory, IO to memory, memory to IO, and IO to IO transfers Burst transfer mode to enhance the transfer rate
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A/D Converter & Touch Screen Interface
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8-ch multiplexed ADC Max. 500KSPS and 10-bit Resolution Internal FET for direct Touch screen interface
Timer with Pulse Width Modulation (PWM)
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4-ch 16-bit Timer with PWM / 1-ch 16-bit internal timer with DMA-based or interrupt-based operation Programmable duty cycle, frequency, and polarity Dead-zone generation Supports external clock sources
LCD Controller STN LCD Displays Feature
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Supports 3 types of STN LCD panels: 4-bit dual scan, 4-bit single scan, 8-bit single scan display type Supports monochrome mode, 4 gray levels, 16 gray levels, 256 colors and 4096 colors for STN LCD Supports multiple screen size
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RTC (Real Time Clock)
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Full clock feature: msec, second, minute, hour, date, day, month, and year 32.768 KHz operation Alarm interrupt Time tick interrupt
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- Maximum screen size: 2048x1024 - Recommended screen size: max 800x600 - Maximum virtual screen size is 4 Mbytes. - Maximum virtual screen size in 256 color mode: 4096x1024, 2048x2048, 1024x4096 and others TFT(Thin Film Transistor) Color Displays Feature
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General Purpose Input/Output Ports
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24 external interrupt ports Multiplexed input/output ports Supports 1, 2, 4 or 8 bpp (bit-per-pixel) palette color displays for color TFT Supports 16 bpp non-palette true-color displays for color TFT Supports maximum 16M color TFT at 24 bpp mode Supports multiple screen size
UART
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3-channel UART with DMA-based or interruptbased operation Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/receive (Tx/Rx) Supports external clocks for the UART operation (UARTCLK) Programmable baud rate Supports IrDA 1.0 Loopback mode for testing Each channel has internal 64-byte Tx FIFO and
- Maximum screen size: 2048x1024 - Recommended screen size: max 800x600 - Maximum virtual screen size is 4Mbytes. - Maximum virtual screen size in 64K color mode: 2048x1024, and others
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
PRODUCT OVERVIEW
S3C2440X
FEATURES (Continued)
Watchdog Timer
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Compatible with SDIO Card Protocol version 1.0 Bytes FIFO for Tx/Rx DMA based or Interrupt based operation Compatible with Multimedia Card Protocol version 2.11
16-bit Watchdog Timer Interrupt request or system reset at time-out
IIC-Bus Interface
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1-ch Multi-Master IIC-Bus Serial, 8-bit oriented and bi-directional data transfers can be made at up to 100 Kbit/s in Standard mode or up to 400 Kbit/s in Fast mode. SPI Interface
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Compatible with 2-ch Serial Peripheral Interface Protocol version 2.11 2x8 bits Shift register for Tx/Rx DMA-based or interrupt-based operation
IIS-Bus Interface
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1-ch IIS-bus for audio interface with DMA-based operation Serial, 8-/16-bit per channel data transfers 128 Bytes (64-Byte + 64-Byte) FIFO for Tx/Rx Supports IIS format and MSB-justified data format
Camera Interface
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ITU601/ITU656-format input support (8-bit) YCrCb 4:2:2 to 4:2:0 down-sampling Up to 1016 Horizontal resolution support
USB Host
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Operating Voltage Range
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2-port USB Host Complies with OHCI Rev. 1.0 Compatible with USB Specification version 1.1
Core: 1.2V Memory :1.8V/ 2.5V/3.3V I/O : 3.3V
USB Device
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Operating Frequency
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1-port USB Device 5 Endpoints for USB Device Compatible with USB Specification version 1.1
Up to 400MHz
Package
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289-FBGA
SD Host Interface
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Compatible with SD Memory Card Protocol version 1.0
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X
PRODUCT OVERVIEW
BLOCK DIAGRAM
ARM920T
Instruction MMU C13 IV2A[31:0] ARM9TDMI Processor core (Internal Embedded ICE) DD[31:0] DV2A[31:0] C13 Data MMU DPA[31:0] Data CACHE (16KB) WriteBack PA Tag RAM WBPA[31:0] DVA[31:0] ID[31:0] CP15 Write Buffer AMBA Bus I/F
IPA[31:0] Instruction CACHE (16KB) External Coproc Interface
JTAG
LCD CONT.
LCD DMA
USB Host CONT.
A H B B U S
Bridge & DMA (4Ch)
BUS CONT. Arbitor/Decode Interrupt CONT. Power Management Camera Interface Memory CONT. SRAM/NOR/SDRAM
ExtMaster NAND Ctrl. NAND Flash Boot Loader Clock Generator (MPLL) UART 0, 1, 2 USB Device SDI/MMC Watchdog Timer BUS CONT. Arbitor/Decode SPI 0, 1 SPI
I2C
A P B B U S
I2S GPIO RTC ADC Timer/PWM 0 ~ 3, 4(Internal)
Figure 1-1. S3C2440X Block Diagram
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
PRODUCT OVERVIEW
S3C2440X
PIN ASSIGNMENTS
U T R P N M L K J H G F E D C B A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
BOTTOM VIEW
Figure 1-2. S3C2440X Pin Assignments (289-FBGA)
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X
PRODUCT OVERVIEW
Table 1-1. 289-Pin FBGA Pin Assignments - Pin Number Order (Sheet 1 of 3) Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 VDDi SCKE VSSi VSSi VSSMOP VDDi VSSMOP ADDR10 VDDMOP VDDi VSSMOP VSSi DATA3 DATA7 VSSMOP VDDi DATA10 VSSMOP nGCS1/GPA12 SCLK1 SCLK0 nBE1 VDDMOP ADDR2 ADDR9 ADDR12 VSSi VDDi VDDMOP VSSMOP VDDMOP DATA9 VDDMOP DATA15 Pin Name Pin Number C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 Pin Name VDDMOP nGCS5/GPA16 nGCS2/GPA13 nGCS3/GPA14 nOE nSRAS ADDR4 ADDR11 ADDR15 ADDR21/GPA6 ADDR24/GPA9 DATA1 DATA6 DATA11 DATA13 DATA16 VSSi ALE/GPA18 nGCS6 nGCS4/GPA15 nBE0 nBE2 nSCAS ADDR7 ADDR5 ADDR16/GPA1 ADDR20/GPA5 ADDR26/GPA11 DATA0 DATA8 DATA14 DATA12 VSSMOP VSSMOP Pin Number E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 Pin Name nFRE/GPA20 VSSMOP nGCS7 nWAIT nBE3 nWE ADDR1 ADDR6 ADDR14 ADDR23/GPA8 DATA2 DATA20 DATA19 DATA18 DATA17 DATA21 DATA24 VDDi VSSi nFWE/GPA19 nFCE/GPA22 CLE/GPA17 nGCS0 ADDR0/GPA0 ADDR3 ADDR18/GPA3 DATA4 DATA5 DATA27 DATA31 DATA26 DATA22 VDDi VDDMOP
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
PRODUCT OVERVIEW
S3C2440X
Table 1-1. 289-Pin FBGA Pin Assignments - Pin Number Order (Sheet 2 of 3) Pin Number G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 Pin Name VSSOP CAMHREF/GPJ10 CAMDATA1/GPJ1 VDDalive CAMPCLK/GPJ8 FRnB CAMVSYNC/GPJ9 ADDR8 ADDR17/GPA2 ADDR25/GPA10 DATA28 DATA25 DATA23 XTIpll XTOpll DATA29 VSSi VSSiarm CAMDATA7/GPJ7 CAMDATA4/GPJ4 CAMDATA3/GPJ3 CAMDATA2/GPJ2 CAMDATA0/GPJ0 CAMDATA5/GPJ5 ADDR13 ADDR19/GPA4 ADDR22/GPA7 VSSOP1 EXTCLK DATA30 nBATT_FLT nTRST nRESET TDI Pin Number J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 Pin Name VDDOP VDDiarm CAMCLKOUT/GPJ11 CAMRESET/GPJ12 TOUT1/GPB1 TOUT0/GPB0 TOUT2/GPB2 CAMDATA6/GPJ6 SDDAT3/GPE10 EINT10/nSS0/GPG2 TXD2/nRTS1/GPH6 PWREN TCK TMS RXD2/nCTS1/GPH7 TDO VDDalive VSSiarm nXBACK/GPB5 TOUT3/GPB3 TCLK0/GPB4 nXDREQ1/GPB8 nXDREQ0/GPB10 nXDACK1/GPB7 SDCMD/GPE6 SPIMISO0/GPE11
EINT13/SPIMISO1/GPG5
Pin Number L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17
Pin Name LEND/GPC0 VDDiarm nXDACK0/GPB9 VCLK/GPC1 nXBREQ/GPB6 VD1/GPC9 VFRAME/GPC3 I2SSDI/nSS0/GPE3 SPICLK0/GPE13 EINT15/SPICLK1/GPG7 EINT22/GPG14 Xtortc EINT2/GPF2 EINT5/GPF5 EINT6/GPF6 EINT7/GPF7 nRTS0/GPH1 VLINE/GPC2 LCD_LPCREV/GPC6 LCD_LPCOE/GPC5 VM/GPC4 VD9/GPD1 VD6/GPC14 VD16/SPIMISO1/GPD8 SDDAT1/GPE8 IICSDA/GPE15 EINT20/GPG12 EINT17/nRTS1/GPG9 VSSA_UPLL VDDA_UPLL Xtirtc EINT3/GPF3 EINT1/GPF1 EINT4/GPF4
nCTS0/GPH0 VDDOP TXD0/GPH2 RXD0/GPH3 UARTCLK/GPH8 TXD1/GPH4 RXD1/GPH5
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X
PRODUCT OVERVIEW
Table 1-1. 289-Pin FBGA Pin Assignments - Pin Number Order (Sheet 3 of 3) Pin Number N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 Pin Name VSSOP VD0/GPC8 VD4/GPC12 VD2/GPC10 VD10/GPD2 VD15/GPD7 VD22/nSS1/GPD14 SDCLK/GPE5 EINT8/GPG0 EINT18/nCTS1/GPG10 DP0 DN1/PDN0 nRSTOUT/GPA21 MPLLCAP VDD_RTC VDDA_MPLL EINT0/GPF0 LCD_LPCREVB/GPC7 VD5/GPC13 VD7/GPC15 VD12/GPD4 VD14/GPD6
VD20/GPD12
Pin Number R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17
Pin Name VD3/GPC11 VD8/GPD0 VD11/GPD3 VD13/GPD5 VD18/SPICLK1/GPD10 VD21 /GPD13 I2SSCLK/GPE1 SDDAT0/GPE7 CLKOUT0/GPH9 EINT11/nSS1/GPG3
EINT14/SPIMOSI1/GPG6
Pin Number U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17
Pin Name VDDiarm VDDiarm VSSOP VSSiarm VD23/nSS0/GPD15 I2SSDO/I2SSDI/GPE4 VSSiarm IICSCL/GPE14 VSSOP VSSiarm VDDiarm EINT19/TCLK1/GPG11 EINT23/GPG15 DP1/PDP0 VSSOP Vref AIN1
NCON OM1 AIN0 AIN2 AIN6 VSSA_MPLL VSSiarm VSSiarm VDDOP VD17/SPIMOSI1/GPD9 VD19/GPD11 VDDiarm CDCLK/GPE2 VDDiarm EINT9/GPG1 EINT16/GPG8 EINT21/GPG13 VDDOP OM3 VSSA_ADC OM0 AIN4 AIN5
I2SLRCK/GPE0 SDDAT2/GPE9 SPIMOSI0/GPE12 CLKOUT1/GPH10 EINT12/LCD_PWREN DN0 OM2 VDDA_ADC AIN3 AIN7 UPLLCAP
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
PRODUCT OVERVIEW
S3C2440X
Table 1-2. S3C2440X 289-Pin FBGA Pin Assignments (Sheet 1 of 9) Pin Number F7 E7 B7 F8 C7 D8 E8 D7 G8 B8 A8 C8 B9 H8 E9 C9 D9 G9 F9 H9 D10 C10 H10 E10 C11 G10 D11 R14 U17 R15 P15 T16 T17 R16 Pin Name ADDR0/GPA0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16/GPA1 ADDR17/GPA2 ADDR18/GPA3 ADDR19/GPA4 ADDR20/GPA5 ADDR21/GPA6 ADDR22/GPA7 ADDR23/GPA8 ADDR24/GPA9 ADDR25/GPA10 ADDR26/GPA11 AIN0 AIN1 AIN2 AIN3 YM/AIN4 YP/AIN5 XM/AIN6 Default Function ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 ADDR23 ADDR24 ADDR25 ADDR26 AIN0 AIN1 AIN2 AIN3 AIN4 YP AIN6 I/O State @BUS REQ Hi-z/- Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- - - - - -/- -/- -/- I/O State @Sleep O(L)/- O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- - - - - -/- -/- -/- I/O State @nRESET O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) AI AI AI AI AI AI AI I/O Type t10s t10s t10s t10s t10s t10s t10s t10s t10s t10s t10s t10s t10s t10s t10s t10s t10s t10s t10s t10s t10s t10s t10s t10s t10s t10s t10s r10 r10 r10 r10 r10 r10 r10
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X
PRODUCT OVERVIEW
Table 1-2. S3C2440X 289-Pin FBGA Pin Assignments (Sheet 2 of 9) Pin Number P16 H6 G3 H5 H4 H3 H7 J8 H2 G5 G7 G2 J3 J4 D12 C12 E11 A13 F10 F11 C13 A14 D13 B15 A17 C14 D15 C15 D14 B17 C16 E15 E14 Pin Name XP/AIN7 CAMDATA0/GPJ0 CAMDATA1/GPJ1 CAMDATA2/GPJ2 CAMDATA3/GPJ3 CAMDATA4/GPJ4 CAMDATA5/GPJ5 CAMDATA6/GPJ6 CAMDATA7/GPJ7 CAMPCLK/GPJ8 CAMVSYNC/GPJ9 CAMHREF/GPJ10 CAMPCLKOUT/GPJ11 CAMRESET/GPJ12 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DATA16 DATA17 DATA18 Default Function XP GPJ0 GPJ1 GPJ2 GPJ3 GPJ4 GPJ5 GPJ6 GPJ7 GPJ8 GPJ9 GPJ10 GPJ11 GPJ12 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DATA16 DATA17 DATA18 I/O State @BUS REQ -/- -/- -/- -/- -/- -/- -/- -/- -/- -/- -/- -/- -/- -/- Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z I/O State @Sleep -/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- O(L)/- O(L)/- Hi-z,O(L) Hi-z,O(L) Hi-z,O(L) Hi-z,O(L) Hi-z,O(L) Hi-z,O(L) Hi-z,O(L) Hi-z,O(L) Hi-z,O(L) Hi-z,O(L) Hi-z,O(L) Hi-z,O(L) Hi-z,O(L) Hi-z,O(L) Hi-z,O(L) Hi-z,O(L) Hi-z,O(L) Hi-z,O(L) Hi-z,O(L) I/O State @nRESET AI I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I/O Type r10 t8 t8 t8 t8 t8 t8 t8 t8 t8 t8 t8 t8 t8 b12s b12s b12s b12s b12s b12s b12s b12s b12s b12s b12s b12s b12s b12s b12s b12s b12s b12s b12s
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
PRODUCT OVERVIEW
S3C2440X
Table 1-2. S3C2440X 289-Pin FBGA Pin Assignments (Sheet 3 of 9) Pin Number E13 E12 E16 F15 G13 E17 G12 F14 F12 G11 G16 H13 F13 P12 N11 N12 U14 N17 M16 L13 M15 M17 L14 L15 L16 N9 T9 J10 R10 P11 K10 R11 L10 Pin Name DATA19 DATA20 DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 DN0 DP0 DN1/PDN0 DP1/PDP0 EINT0/GPF0 EINT1/GPF1 EINT2/GPF2 EINT3/GPF3 EINT4/GPF4 EINT5/GPF5 EINT6/GPF6 EINT7/GPF7 EINT8/GPG0 EINT9/GPG1 EINT10/nSS0/GPG2 EINT11/nSS1/GPG3 EINT12/LCD_PWREN/GPG4 EINT13/SPIMISO1/GPG5 EINT14/SPIMOSI1/GPG6 EINT15/SPICLK1/GPG7 Default Function DATA19 DATA20 DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 DN0 DP0 DN1 DP1 GPF0 GPF1 GPF2 GPF3 GPF4 GPF5 GPF6 GPF7 GPG0 GPG1 GPG2 GPG3 GPG4 GPG5 GPG6 GPG7 I/O State @BUS REQ Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z -/- -/- -/- -/- -/- -/- -/- -/- -/- -/- -/- -/- -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- I/O State @Sleep Hi-z,O(L) Hi-z,O(L) Hi-z,O(L) Hi-z,O(L) Hi-z,O(L) Hi-z,O(L) Hi-z,O(L) Hi-z,O(L) Hi-z,O(L) Hi-z,O(L) Hi-z,O(L) Hi-z,O(L) Hi-z,O(L) Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/Hi-z/- Hi-z/Hi-z/- Hi-z/O(L)/- Hi-z/Hi-z/- Hi-z/Hi-z/- Hi-z/Hi-z/- I/O State @nRESET I I I I I I I I I I I I I AI AI AI AI I I I I I I I I I I I I I I I I I/O Type b12s b12s b12s b12s b12s b12s b12s b12s b12s b12s b12s b12s b12s us us us us t8 t8 t8 t8 t8 t8 t8 t8 t8 t8 t8 t8 t8 tt8 tt8 tt8
1-12
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X
PRODUCT OVERVIEW
Table 1-2. S3C2440X 289-Pin FBGA Pin Assignments (Sheet 4 of 9) Pin Number T10 M11 N10 U12 M10 T11 L11 U13 H12 P17 N14 H14 D4 B5 D5 E5 R12 G6 F3 E1 F4 F5 D1 N13 C5 H16 F6 B2 C3 C4 D3 C2 D2 Pin Name EINT16/GPG8 EINT17/nRTS1/GPG9 EINT18/nCTS1/GPG10 EINT19/TCLK1/GPG11 EINT20/GPG12 EINT21/GPG13 EINT22/GPG14 EINT23/GPG15 EXTCLK UPLLCAP MPLLCAP nBATT_FLT nBE0 nBE1 nBE2 nBE3 NCON FRnB nFWE/GPA19 nFRE/GPA20 nFCE/GPA22 CLE/GPA17 ALE/GPA18 nRSTOUT/GPA21 nOE nRESET nGCS0 nGCS1/GPA12 nGCS2/GPA13 nGCS3/GPA14 nGCS4/GPA15 nGCS5/GPA16 nGCS6 Default Function GPG8 GPG9 GPG10 GPG11 GPG12 GPG13 GPG14 GPG15 EXTCLK UPLLCAP MPLLCAP nBATT_FLT nBE0 nBE1 nBE2 nBE3 NCON FRnB GPA19 GPA20 GPA21 GPA17 GPA18 GPA21 nOE nRESET nGCS0 GPA12 GPA13 GPA14 GPA15 GPA16 nGCS6 I/O State @BUS REQ -/- -/-/- -/-/- -/-/- -/- -/- -/- -/- - - - - Hi-z Hi-z Hi-z Hi-z - - O(H)/- O(H)/- O(H)/- O(L)/- O(L)/- -/- Hi-z - Hi-z Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z I/O State @Sleep Hi-z/- Hi-z/O(H)/- Hi-z/Hi-z/- Hi-z/Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- - - - - Hi-z,O(H) Hi-z,O(H) Hi-z,O(H) Hi-z,O(H) - Hi-z,O(L) Hi-z,O(H)/- Hi-z,O(H)/- Hi-z,O(H)/- Hi-z,O(L)/- Hi-z,O(L)/- O(L)/- Hi-z,O(H) - Hi-z,O(H) Hi-z,O(H)/- Hi-z,O(H)/- Hi-z,O(H)/- Hi-z,O(H)/- Hi-z,O(H)/- Hi-z,O(H) I/O State @nRESET I I I I I I I I AI AI AI I O(H) O(H) O(H) O(H) I I O(H) O(H) O(H) O(L) O(L) O(L) O(H) I O(H) O(H) O(H) O(H) O(H) O(H) O(H) I/O Type t8 t8 t8 t12 t12 t12 t12 t12 is r50 r50 is t10s t10s t10s t10s is d2s t10s t10s t10s t10s t10s b8 t10s is t10s t10s t10s t10s t10s t10s t10s
1-13
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
PRODUCT OVERVIEW
S3C2440X
Table 1-2. S3C2440X 289-Pin FBGA Pin Assignments (Sheet 5 of 9) Pin Number E3 D6 C6 H15 E4 E6 J6 J5 J7 K3 K4 K2 L5 K7 K5 L3 K6 T15 R13 P13 T13 J12 K11 L17 K13 K14 K16 K17 J11 J15 K15 R9 P10 Pin Name nGCS7 nSCAS nSRAS nTRST nWAIT nWE TOUT0/GPB0 TOUT1/GPB1 TOUT2/GPB2 TOUT3/GPB3 TCLK0/GPB4 nXBACK/GPB5 nXBREQ/GPB6 nXDACK1/GPB7 nXDREQ1/GPB8 nXDACK0/GPB9 nXDREQ0/GPB10 OM0 OM1 OM2 OM3 PWREN nCTS0/GPH0 nRTS0/GPH1 TXD0/GPH2 RXD0/GPH3 TXD1/GPH4 RXD1/GPH5 TXD2/nRTS1/GPH6 RXD2/nCTS1/GPH7 UARTCLK/GPH8 CLKOUT0/GPH9 CLKOUT1/GPH10 Default Function nGCS7 nSCAS nSRAS nTRST nWAIT nWE GPB0 GPB1 GPB2 GPB3 GPB4 GPB5 GPB6 GPB7 GPB8 GPB9 GPB10 OM0 OM1 OM2 OM3 PWREN GPH0 GPH1 GPH2 GPH3 GPH4 GPH5 GPH6 GPH7 GPH8 GPH9 GPH10 I/O State @BUS REQ Hi-z Hi-z Hi-z I - Hi-z -/- -/- -/- -/- -/- -/- -/- -/- -/- -/- -/- - - - - O(H) -/- -/- -/- -/- -/- -/- -/-/- -/-/- -/- -/- -/- I/O State @Sleep Hi-z,O(H) Hi-z,O(H) Hi-z,O(H) - Hi-z,O(L) Hi-z,O(H) O(L)/- O(L)/- O(L)/- O(L)/- -/- O(H)/- -/- O(H)/- -/- O(H)/- -/- - - - - O(L) -/- O(H)/- O(H)/- -/- O(H)/- -/- O(H)/O(H)/- Hi-z/Hi-z/- Hi-z/- O(L)/- O(L)/- I/O State @nRESET O(H) O(H) O(H) I I O(H) I I I I I I I I I I I I I I I O(H) I I I I I I I I I I I I/O Type t10s t10s t10s is d2s t10s t8 t8 t8 t8 t8 t8 t8 t8 t8 t8 t8 is is is is b8 t8 t8 t8 t8 t8 t8 t8 t8 t8 t12 t12
1-14
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X
PRODUCT OVERVIEW
Table 1-2. S3C2440X 289-Pin FBGA Pin Assignments (Sheet 6 of 9) Pin Number A2 B4 B3 P7 R7 T7 L8 U6 N8 K8 R8 M8 P8 J9 K9 P9 L9 U8 M9 J13 H17 J16 J14 L1 L4 M1 L7 M4 M3 M2 P1 N2 L6 Pin Name SCKE SCLK0 SCLK1 I2SLRCK/GPE0 I2SSCLK/GPE1 CDCLK/GPE2 I2SSDI/nSS0/GPE3 I2SSDO/I2SSDI/GPE4 SDCLK/GPE5 SDCMD/GPE6 SDDAT0/GPE7 SDDAT1/GPE8 SDDAT2/GPE9 SDDAT3/GPE10 SPIMISO0/GPE11 SPIMOSI0/GPE12 SPICLK0/GPE13 IICSCL/GPE14 IICSDA/GPE15 TCK TDI TDO TMS LEND/GPC0 VCLK/GPC1 VLINE/GPC2 VFRAME/GPC3 VM/GPC4 LCD_LPCOE/GPC5 LCD_LPCREV/GPC6 LCD_LPCREVB/GPC7 VD0/GPC8 VD1/GPC9 Default Function SCKE SCLK0 SCLK1 GPE0 GPE1 GPE2 GPE3 GPE4 GPE5 GPE6 GPE7 GPE8 GPE9 GPE10 GPE11 GPE12 GPE13 GPE14 GPE15 TCK TDI TDO TMS GPC0 GPC1 GPC2 GPC3 GPC4 GPC5 GPC6 GPC7 GPC8 GPC9 I/O State @BUS REQ Hi-z Hi-z Hi-z -/- -/- -/- -/-/- -/-/- -/- -/- -/- -/- -/- -/- -/- -/- -/- -/- -/- I I O I -/- -/- -/- -/- -/- -/- -/- -/- -/- -/- I/O State @Sleep O(L) O(L) O(L) Hi-z/- Hi-z/- Hi-z/- Hi-z/Hi-z/- O(L)/Hi-z/- O(L)/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- - - O - O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- I/O State @nRESET O(H) O(SCLK) O(SCLK) I I I I I I I I I I I I I I I I I I O I I I I I I I I I I I I/O Type t10s t12s t12s t8 t8 t8 t8 t8 t8 t8 t8 t8 t8 t8 tt8 tt8 tt8 d8 d8 is is ot is t8 t8 t8 t8 t8 t8 t8 t8 t8 t8
1-15
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
PRODUCT OVERVIEW
S3C2440X
Table 1-2. S3C2440X 289-Pin FBGA Pin Assignments (Sheet 7 of 9) Pin Number N4 R1 N3 P2 M6 P3 R2 M5 N5 R3 P4 R4 P5 N6 M7 T4 R5 T5 P6 R6 N7 U5 U16 G14 M14 G15 L12 N15 P14 N16 M13 G4 J17 Pin Name VD2/GPC10 VD3/GPC11 VD4/GPC12 VD5/GPC13 VD6/GPC14 VD7/GPC15 VD8/GPD0 VD9/GPD1 VD10/GPD2 VD11/GPD3 VD12/GPD4 VD13/USBTXDN1/GPD5 VD14/USBTXDP1/GPD6 VD15/USBOEN1/GPD7 VD16/SPIMISO1/GPD8 VD17/SPIMOSI1/GPD9 VD18/SPICLK1/GPD10 VD19/USBRXDP1/GPD11 VD20/USBRXDN1/GPD12 VD21/USBRXD1/GPD13 VD22/nSS1/GPD14 VD23/nSS0/GPD15 Vref XTIpll Xtirtc XTOpll Xtortc VDD_RTC VDDA_ADC VDDA_MPLL VDDA_UPLL VDDalive VDDalive Default Function GPC10 GPC11 GPC12 GPC13 GPC14 GPC15 GPD0 GPD1 GPD2 GPD3 GPD4 GPD5 GPD6 GPD7 GPD8 GPD9 GPD10 GPD11 GPD12 GPD13 GPD14 GPD15 Vref XTIpll Xtirtc XTOpll Xtortc VDD_RTC VDDA_ADC VDDA_MPLL VDDA_UPLL VDDalive VDDalive I/O State @BUS REQ -/- -/- -/- -/- -/- -/- -/- -/- -/- -/- -/- -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- - - - - - P P P P P P I/O State @Sleep O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- O(L)/O/- O(L)/O/- O(L)/O/- O(L)/Hi-z/- O(L)/Hi-z/- O(L)/Hi-z/- O(L)/Hi-z/- O(L)/Hi-z/- O(L)/Hi-z/- O(L)/Hi-z/- O(L)/Hi-z/- - - - - - P P P P P P I/O State @nRESET I I I I I I I I I I I I I I I I I I I I I I AI AI AI AO AO P P P P P P I/O Type t8 t8 t8 t8 t8 t8 t8 t8 t8 t8 t8 t8 t8 t8 tt8 tt8 tt8 t8 t8 t8 t8 t8 ia m26 nc m26 nc drtc d33t d33t d33t d12i d12i
1-16
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X
PRODUCT OVERVIEW
Table 1-2. S3C2440X 289-Pin FBGA Pin Assignments (Sheet 8 of 9) Pin Number A1 A10 A16 A6 B11 F1 F16 J2 L2 T6 T8 U1 U11 U2 A9 B12 B14 B16 B6 C1 F17 J1 T12 T3 K12 T14 R17 M12 A12 A3 A4 B10 C17 Pin Name VDDi VDDi VDDi VDDi VDDi VDDi VDDi VDDiarm VDDiarm VDDiarm VDDiarm VDDiarm VDDiarm VDDiarm VDDMOP VDDMOP VDDMOP VDDMOP VDDMOP VDDMOP VDDMOP VDDOP VDDOP VDDOP VDDOP VSSA_ADC VSSA_MPLL VSSA_UPLL VSSi VSSi VSSi VSSi VSSi Default Function VDDi VDDi VDDi VDDi VDDi VDDi VDDi VDDiarm VDDiarm VDDiarm VDDiarm VDDiarm VDDiarm VDDiarm VDDMOP VDDMOP VDDMOP VDDMOP VDDMOP VDDMOP VDDMOP VDDOP VDDOP VDDOP VDDOP VSSA_ADC VSSA_MPLL VSSA_UPLL VSSi VSSi VSSi VSSi VSSi I/O State @BUS REQ P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P I/O State @Sleep P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P I/O State @nRESET P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P I/O Type d12c d12c d12c d12c d12c d12c d12c d12c d12c d12c d12c d12c d12c d12c d33o d33o d33o d33o d33o d33o d33o d33o d33o d33o d33o st st st si si si si si
1-17
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
PRODUCT OVERVIEW
S3C2440X
Table 1-2. S3C2440X 289-Pin FBGA Pin Assignments (Sheet 9 of 9) Pin Number F2 G17 H1 K1 T1 T2 U10 U4 U7 A11 A15 A5 A7 B1 B13 D16 D17 E2 G1 N1 U15 U3 U9 H11 Pin Name VSSi VSSi VSSiarm VSSiarm VSSiarm VSSiarm VSSiarm VSSiarm VSSiarm VSSMOP VSSMOP VSSMOP VSSMOP VSSMOP VSSMOP VSSMOP VSSMOP VSSMOP VSSOP VSSOP VSSOP VSSOP VSSOP VSSOP Default Function VSSi VSSi VSSiarm VSSiarm VSSiarm VSSiarm VSSiarm VSSiarm VSSiarm VSSMOP VSSMOP VSSMOP VSSMOP VSSMOP VSSMOP VSSMOP VSSMOP VSSMOP VSSOP VSSOP VSSOP VSSOP VSSOP VSSOP I/O State @BUS REQ P P P P P P P P P P P P P P P P P P P P P P P P I/O State @Sleep P P P P P P P P P P P P P P P P P P P P P P P P I/O State @nRESET P P P P P P P P P P P P P P P P P P P P P P P P I/O Type si si si si si si si si si so so so so so so so so so so so so so so so
1-18
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X
PRODUCT OVERVIEW
NOTE: 1. The @BUS REQ. shows the pin state at the external bus, which is used by the other bus master. 2. ' - ` mark indicates the unchanged pin state at Bus Request mode. 3. Hi-z or Pre means Hi-z or early state and it is determined by the setting of MISCCR register. 4. AI/AO means analog input/analog output. 5. P, I, and O mean power, input and output respectively. 6. The I/O state @nRESET shows the pin status in the @nRESET duration below.
4FCLK nRESET
@nRESET
FCLK
1-19
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
PRODUCT OVERVIEW
S3C2440X
7.
The table below shows I/O types and the descriptions.
I/O Type d12i(vdd12ih) d12c(vdd12ih_core), si(vssih) d33o(vdd33oph), so(vssoph) 1.2V Vdd for alive power 1.2V Vdd/Vss for internal logic
Descriptions
3.3V Vdd/Vss for external logic
d33t(vdd33th_abb), st(vssbbh_abb) 3.3V Vdd/Vss for analog circuitry drtc(vdd30th_rtc) t8(phbsu100ct8sm) is(phis) us(pbusb0) t10(phtot10cd) ot(phot8) b8(phob8) t16(phot16sm) r10(phiar10_abb) ia(phia_abb) gp(phgpad_option) m26(phsoscm26_2440) tt8(phtbsu100ct8sm) t12(phbsu100ct12sm) d2(phtod2) d8(phbsd8sm) t10s(phtot10cd_10_2440x) b12s(phtbsu100ct12cd_12_2440x) d2s(phtbsd2_2440x) r50(phoar50_abb) t12s(phtot12cd_12_2440x) nc(phnc) 3.0V Vdd for RTC power Bi-directional pad, LVCMOS schmitt-trigger, 100Kohm pull-up resistor with control, tri-state, Io=8mA Input pad, LVCMOS schmitt-trigger level USB pad 5V tolerant Output pad, Tri-state . Output pad, tri-state, Io=8mA Output pad, Io=8mA Output pad, tri-state, medium slew rate, Io=16mA Analog input pad with 10-ohm resistor Analog input pad Pad for analog pin Oscillator cell with enable and feedback resistor 5V Tolerant Bi-directional pad, LVCMOS schmitt-trigger, 100Kohm pull-up resistor with control, tri -state, medium slew rate, Io=8mA Bi-directional pad, LVCMOS schmitt-trigger, 100Kohm pull-up resistor with control, tri-state, Io=12mA 5v tolerant Output pad , Open Drain , Io=2mA Bi-directional pad, LVCMOS schmitt-trigger, Open Drain, Io=8mA 5V Tolerant output pad, LVCMOS , tri -state, output drive strenth control, Io=4,6,8,10mA 5V Tolerant Bi-directional pad, LVCMOS schmitt-trigger, 100Kohm pull-up resistor with control, tri -state,output drive strenth control, Io=6,8,10,12mA 5V Tolerant Bi-directional pad, LVCMOS schmitt-trigger, open-drain, output drive strenth ignore, Analog Output pad, 50Kohm resistor, Separated bulk-bias 5V Tolerant output pad, LVCMOS , tri -state, output drive strenth control, Io=6,8,12,16mA No connection pad
1-20
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X
PRODUCT OVERVIEW
SIGNAL DESCRIPTIONS Table 1-3. S3C2440X Signal Descriptions (Sheet 1 of 6) Signal Bus Controller OM[1:0] I OM[1:0] sets S3C2440X in the TEST mode, which is used only at fabrication. Also, it determines the bus width of nGCS0. The pull-up/down resistor determines the logic level during RESET cycle. 00:Nand-boot ADDR[26:0] DATA[31:0] nGCS[7:0] O IO O 01:16-bit 10:32-bit 11:Test mode ADDR[26:0] (Address Bus) outputs the memory address of the corresponding bank . DATA[31:0] (Data Bus) inputs data during memory read and outputs data during memory write. The bus width is programmable among 8/16/32-bit. nGCS[7:0] (General Chip Select) are activated when the address of a memory is within the address region of each bank. The number of access cycles and the bank size can be programmed. nWE (Write Enable) indicates that the current bus cycle is a write cycle. nOE (Output Enable) indicates that the current bus cycle is a read cycle. nXBREQ (Bus Hold Request) allows another bus master to request control of the local bus. BACK active indicates that bus control has been granted. nXBACK (Bus Hold Acknowledge) indicates that the S3C2440X has surrendered control of the local bus to another bus master. nWAIT requests to prolong a current bus cycle. As long as nWAIT is L, the current bus cycle cannot be completed. SDRAM Row Address Strobe SDRAM Column Address Strobe SDRAM Chip Select SDRAM Data Mask SDRAM Clock SDRAM Clock Enable Upper Byte/Lower Byte Enable(In case of 16-bit SRAM) Write Byte Enable Command Latch Enable Address Latch Enable Nand Flash Chip Enable Nand Flash Read Enable Nand Flash Write Enable Nand Flash Configuration Nand Flash Ready/Busy * If NAND flash controller isn't used, it has to be pull-up. (3.3V) I/O Descriptions
nWE nOE nXBREQ nXBACK nWAIT SDRAM/SRAM nSRAS nSCAS nSCS[1:0] DQM[3:0] SCLK[1:0] SCKE nBE[3:0] nWBE[3:0] NAND Flash CLE ALE nFCE nFRE nFWE NCON FRnB
O O I O I
O O O O O O O O O O O O O I I
1-21
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
PRODUCT OVERVIEW
S3C2440X
Table 1-3. S3C2440X Signal Descriptions (Sheet 2 of 6) Signal LCD Control Unit VD[23:0] LCD_PWREN VCLK VFRAME VLINE VM VSYNC HSYNC VDEN LEND STV CPV LCD_HCLK TP STH LCD_LPCOE LCD_LPCREV LCD_LPCREVB CAMERA Interface CAMRESET CAMCLKOUT CAMPCLK CAMHREF CAMVSYNC CAMDATA[7:0] EINT[23:0] DMA nXDREQ[1:0] nXDACK[1:0] I O External DMA request External DMA acknowledge O O I I I I I Software Reset to the Camera Master Clock to the Camera Pixel clock from Camera Horizontal sync signal from Camera Vertical sync signal from Camera Pixel data for YCbCr External Interrupt request O O O O O O O O O O O O O O O O O O STN/TFT/SEC TFT: LCD Data Bus STN/TFT/SEC TFT: LCD panel power enable control signal STN/TFT: LCD clock signal STN: LCD Frame signal STN: LCD line signal STN: VM alternates the polarity of the row and column voltage TFT: Vertical synchronous signal TFT: Horizontal synchronous signal TFT: Data enable signal TFT: Line End signal SEC TFT: SEC(Samsung Electronics Company) TFT LCD panel control signal SEC TFT: SEC(Samsung Electronics Company) TFT LCD panel control signal SEC TFT: SEC(Samsung Electronics Company) TFT LCD panel control signal SEC TFT: SEC(Samsung Electronics Company) TFT LCD panel control signal SEC TFT: SEC(Samsung Electronics Company) TFT LCD panel control signal SEC TFT: Timing control signal for specific TFT LCD SEC TFT: Timing control signal for specific TFT LCD SEC TFT: Timing control signal for specific TFT LCD I/O Descriptions
Interrupt Control Unit
1-22
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X
PRODUCT OVERVIEW
Table 1-3. S3C2440X Signal Descriptions (Sheet 3 of 6) Signal UART RxD[2:0] TxD[2:0] nCTS[1:0] nRTS[1:0] UARTCLK ADC AIN[7:0] Vref IIC-Bus IICSDA IICSCL IIS-Bus I2SLRCK I2SSDO I2SSDI I2SSCLK CDCLK Touch Screen nXPON XMON nYPON YMON USB Host DN[1:0] DP[1:0] USB Device PDN0 PDP0 SPI SPIMISO[1:0] SPIMOSI[1:0] SPICLK[1:0] nSS[1:0] IO IO IO I SPIMISO is the master data input line, when SPI is configured as a master. When SPI is configured as a slave, these pins reverse its role. SPIMOSI is the master data output line, when SPI is configured as a master. When SPI is configured as a slave, these pins reverse its role. SPI clock SPI chip select(only for slave mode) IO IO DATA(-) for USB peripheral DATA(+) for USB peripheral IO IO DATA(-) from USB host DATA(+) from USB host O O O O Plus X-axis on-off control signal Minus X-axis on-off control signal Plus Y-axis on-off control signal Minus Y-axis on-off control signal IO O I IO O IIS-bus channel select clock IIS-bus serial data output IIS-bus serial data input IIS-bus serial clock CODEC system clock IO IO IIC-bus data IIC-bus clock AI AI ADC input[7:0]. If it isn't used pin, it has to be Low (Ground). ADC Vref I O I O I UART receives data input UART transmits data output UART clear to send input signal UART request to send output signal UART clock signal I/O Descriptions
1-23
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
PRODUCT OVERVIEW
S3C2440X
Table 1-3. S3C2440X Signal Descriptions (Sheet 4 of 6) Signal SD SDDAT[3:0] SDCMD SDCLK General Port GPn[116:0] TIMMER/PWM TOUT[3:0] TCLK[1:0] JTAG TEST LOGIC nTRST I nTRST(TAP Controller Reset) resets the TAP controller at start. If debugger is used, A 10K pull-up resistor has to be connected. If debugger(black ICE) is not used, nTRST pin must be issued by a low active pulse(Typically connected to nRESET). TMS (TAP Controller Mode Select) controls the sequence of the TAP controller's states. A 10K pull-up resistor has to be connected to TMS pin. TCK (TAP Controller Clock) provides the clock input for the JTAG logic. A 10K pull-up resistor must be connected to TCK pin. TDI (TAP Controller Data Input) is the serial input for test instructions and data. A 10K pull-up resistor must be connected to TDI pin. TDO (TAP Controller Data Output) is the serial output for test instructions and data. O I Timer output[3:0] External timer clock input IO General input/output ports (some ports are output only) IO IO O SD receive/transmit data SD receive response/ transmit command SD clock I/O Description
TMS TCK TDI TDO
I I I O
1-24
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X
PRODUCT OVERVIEW
Table 1-3. S3C2440X Signal Descriptions (Sheet 5 of 6) Signal XTOpll I/O AO Description Crystal Output for internal osc circuit. When OM[3:2] = 00b, XTIpll is used for MPLL CLK source and UPLL CLK source. When OM[3:2] = 01b, XTIpll is used for MPLL CLK source only. When OM[3:2] = 10b, XTIpll is used for UPLL CLK source only. If it isn't used, it has to be a floating pin. Loop filter capacitor for main clock. Loop filter capacitor for USB clock. 32 kHz crystal input for RTC. If it isn't used, it has to be High (3.3V). 32 kHz crystal output for RTC. If it isn't used, it has to be Float. Clock output signal. The CLKSEL of MISCCR register configures the clock output mode among the MPLL CLK, UPLL CLK, FCLK, HCLK, PCLK. nRESET suspends any operation in progress and places S3C2440X into a known reset state. For a reset, nRESET must be held to L level for at least 4 FCLK after the processor power has been stabilized. For external device reset control(nRSTOUT = nRESET & nWDTRST & SW_RESET) 1.2V core power on-off control signal Probe for battery state(Does not wake up at Sleep mode in case of low battery state). If it isn't used, it has to be High (3.3V). OM[3:2] determines how the clock is made. OM[3:2] = 00b, Crystal is used for MPLL CLK source and UPLL CLK source. OM[3:2] = 01b, Crystal is used for MPLL CLK source and EXTCLK is used for UPLL CLK source. OM[3:2] = 10b, EXTCLK is used for MPLL CLK source and Crystal is used for UPLL CLK source. OM[3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK source. EXTCLK I External clock source. When OM[3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK source. When OM[3:2] = 10b, EXTCLK is used for MPLL CLK source only. When OM[3:2] = 01b, EXTCLK is used for UPLL CLK source only. If it isn't used, it has to be High (3.3V). Crystal Input for internal osc circuit. When OM[3:2] = 00b, XTIpll is used for MPLL CLK source and UPLL CLK source. When OM[3:2] = 01b, XTIpll is used for MPLL CLK source only. When OM[3:2] = 10b, XTIpll is used for UPLL CLK source only. If it isn't used, XTIpll has to be High (3.3V).
Reset, Clock & Power
MPLLCAP UPLLCAP XTIrtc XTOrtc CLKOUT[1:0] nRESET
AI AI AI AO O ST
nRSTOUT PWREN nBATT_FLT OM[3:2]
O O I I
XTIpll
AI
1-25
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
PRODUCT OVERVIEW
S3C2440X
Table 1-3. S3C2440X Signal Descriptions (Sheet 6 of 6) Signal Power VDDalive VDDi/VDDiarm VSSi/VSSiarm VDDi_MPLL VSSi_MPLL VDDOP VDDMOP P P P P P P P S3C2440X reset block and port status register VDD(1.2V). It should be always supplied whether in normal mode or in Sleep mode. S3C2440X core logic VDD(1.2V) for CPU. S3C2440X core logic VSS S3C2440X MPLL analog and digital VDD (1.2 V). S3C2440X MPLL analog and digital VSS. S3C2440X I/O port VDD(3.3V) S3C2440X Memory I/O VDD 3.3V : SCLK up to 100MHz 2.5V : SCLK up to 80MHz VSSOP RTCVDD VDDi_UPLL VSSi_UPLL VDDA_ADC VSSA_ADC P P P P P P S3C2440X I/O port VSS RTC VDD (3.0V) (This pin must be connected to power properly if RTC isn't used) S3C2440X UPLL analog and digital VDD (1.2V) S3C2440X UPLL analog and digital VSS S3C2440X ADC VDD(3.3V) S3C2440X ADC VSS I/O Description
NOTE: 1. I/O means input/output. 2. AI/AO means analog input/analog output. 3. ST means schmitt-trigger. 4. P means power.
1-26
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X
PRODUCT OVERVIEW
S3C2440X SPECIAL REGISTERS Table 1-4. S3C2440X Special Registers (Sheet 1 of 14) Register Name Memory Controller BWSCON BANKCON0 BANKCON1 BANKCON2 BANKCON3 BANKCON4 BANKCON5 BANKCON6 BANKCON7 REFRESH BANKSIZE MRSRB6 MRSRB7 0x48000000 0x48000004 0x48000008 0x4800000C 0x48000010 0x48000014 0x48000018 0x4800001C 0x48000020 0x48000024 0x48000028 0x4800002C 0x48000030 W R/W Bus Width & Wait Status Control Boot ROM Control BANK1 Control BANK2 Control BANK3 Control BANK4 Control BANK5 Control BANK6 Control BANK7 Control DRAM/SDRAM Refresh Control Flexible Bank Size Mode register set for SDRAM BANK6 Mode register set for SDRAM BANK7 Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function
1-27
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
PRODUCT OVERVIEW
S3C2440X
Table 1-4. S3C2440X Special Registers (Sheet 2 of 14) Register Name USB Host Controller HcRevision HcControl HcCommonStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCuttentED HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDoneHead HcRmInterval HcFmRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus1 HcRhPortStatus2 Interrupt Controller SRCPND INTMOD INTMSK PRIORITY INTPND INTOFFSET SUBSRCPND INTSUBMSK 0X4A000000 0X4A000004 0X4A000008 0X4A00000C 0X4A000010 0X4A000014 0X4A000018 0X4A00001C W R/W W R/W W R/W R R/W R/W Interrupt Request Status Interrupt Mode Control Interrupt Mask Control IRQ Priority Control Interrupt Request Status Interrupt request source offset Sub source pending Interrupt sub mask 0x49000000 0x49000004 0x49000008 0x4900000C 0x49000010 0x49000014 0x49000018 0x4900001C 0x49000020 0x49000024 0x49000028 0x4900002C 0x49000030 0x49000034 0x49000038 0x4900003C 0x49000040 0x49000044 0x49000048 0x4900004C 0x49000050 0x49000054 0x49000058 Root Hub Group Frame Counter Group Memory Pointer Group
Address (B. Endian)
Address (L. Endian)
Acc. Unit W
Read/ Write
Function
Control and Status Group
1-28
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X
PRODUCT OVERVIEW
Table 1-4. S3C2440X Special Registers (Sheet 3 of 14) Register Name DMA DISRC0 DISRCC0 DIDST0 DIDSTC0 DCON0 DSTAT0 DCSRC0 DCDST0 DMASKTRIG0 DISRC1 DISRCC1 DIDST1 DIDSTC1 DCON1 DSTAT1 DCSRC1 DCDST1 DMASKTRIG1 DISRC2 DISRCC2 DIDST2 DIDSTC2 DCON2 DSTAT2 DCSRC2 DCDST2 DMASKTRIG2 DISRC3 DISRCC3 DIDST3 DIDSTC3 DCON3 DSTAT3 DCSRC3 DCDST3 DMASKTRIG3 0x4B000000 0x4B000004 0x4B000008 0x4B00000C 0x4B000010 0x4B000014 0x4B000018 0x4B00001C 0x4B000020 0x4B000040 0x4B000044 0x4B000048 0x4B00004C 0x4B000050 0x4B000054 0x4B000058 0x4B00005C 0x4B000060 0x4B000080 0x4B000084 0x4B000088 0x4B00008C 0x4B000090 0x4B000094 0x4B000098 0x4B00009C 0x4B0000A0 0x4B0000C0 0x4B0000C4 0x4B0000C8 0x4B0000CC 0x4B0000D0 0x4B0000D4 0x4B0000D8 0x4B0000DC 0x4B0000E0 R/W R

Address (B. Endian)
Address (L. Endian)
Acc. Unit W
Read/ Write R/W
Function
DMA 0 Initial Source DMA 0 Initial Source Control DMA 0 Initial Destination DMA 0 Initial Destination Control DMA 0 Control
R
DMA 0 Count DMA 0 Current Source DMA 0 Current Destination
R/W
DMA 0 Mask Trigger DMA 1 Initial Source DMA 1 Initial Source Control DMA 1 Initial Destination DMA 1 Initial Destination Control DMA 1 Control
R
DMA 1 Count DMA 1 Current Source DMA 1 Current Destination
R/W
DMA 1 Mask Trigger DMA 2 Initial Source DMA 2 Initial Source Control DMA 2 Initial Destination DMA 2 Initial Destination Control DMA 2 Control
R
DMA 2 Count DMA 2 Current Source DMA 2 Current Destination
R/W W R/W
DMA 2 Mask Trigger DMA 3 Initial Source DMA 3 Initial Source Control DMA 3 Initial Destination DMA 3 Initial Destination Control DMA 3 Control DMA 3 Count DMA 3 Current Source DMA 3 Current Destination DMA 3 Mask Trigger
1-29
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
PRODUCT OVERVIEW
S3C2440X
Table 1-4. S3C2440X Special Registers (Sheet 4 of 14) Register Name LOCKTIME MPLLCON UPLLCON CLKCON CLKSLOW CLKDIVN CAMDIVN LCD Controller LCDCON1 LCDCON2 LCDCON3 LCDCON4 LCDCON5 LCDSADDR1 LCDSADDR2 LCDSADDR3 REDLUT GREENLUT BLUELUT DITHMODE TPAL LCDINTPND LCDSRCPND LCDINTMSK TCONSEL 0X4D000000 0X4D000004 0X4D000008 0X4D00000C 0X4D000010 0X4D000014 0X4D000018 0X4D00001C 0X4D000020 0X4D000024 0X4D000028 0X4D00004C 0X4D000050 0X4D000054 0X4D000058 0X4D00005C 0X4D000060 W R/W LCD Control 1 LCD Control 2 LCD Control 3 LCD Control 4 LCD Control 5 STN/TFT: Frame Buffer Start Address1 STN/TFT: Frame Buffer Start Address2 STN/TFT: Virtual Screen Address Set STN: Red Lookup Table STN: Green Lookup Table STN: Blue Lookup Table STN: Dithering Mode TFT: Temporary Palette LCD Interrupt Pending LCD Interrupt Source LCD Interrupt Mask TCON(LPC3600/LCC3600) Control Address (B. Endian) 0x4C000000 0x4C000004 0x4C000008 0x4C00000C 0x4C000010 0x4C000014 0x4C000018 Address (L. Endian) Acc. Unit W Read/ Write R/W Function
Clock & Power Management PLL Lock Time Counter MPLL Control UPLL Control Clock Generator Control Slow Clock Control Clock divider Control Camera Clock divider Control
1-30
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X
PRODUCT OVERVIEW
Table 1-4. S3C2440X Special Registers (Sheet 5 of 14) Register Name NAND Flash NFCONF NFCONT NFCMD NFADDR NFDATA NFMECC0 NFMECC1 NFSECC NFSTAT NFESTAT0 NFESTAT1 NFMECC0 NFMECC1 NFSECC NFSBLK NFEBLK 0x4E000000 0x4E000004 0x4E000008 0x4E00000C 0x4E000010 0x4E000014 0x4E000018 0x4E00001C 0x4E000020 0x4E000024 0x4E000028 0x4E00002C 0x4E000030 0x4E000034 0x4E000038 0x4E00003C R/W R
Address (B. Endian)
Address (L. Endian)
Acc. Unit W
Read/ Write R/W
Function
NAND Flash Configuration NAND Flash Control NAND Flash Command NAND Flash Address NAND Flash Data NAND Flash Main area ECC0/1 NAND Flash Main area ECC2/3 NAND Flash Spare area ECC NAND Flash Operation Status NAND Flash ECC Status for I/O[7:0] NAND Flash ECC Status for I/O[15:8] NAND Flash Main area ECC0 status NAND Flash Main Area ECC1 status NAND Flash Spare Area ECC status NAND Flash start block address NAND Flash end block address
1-31
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
PRODUCT OVERVIEW
S3C2440X
Table 1-4. S3C2440X Special Registers (Sheet 6 of 14) Register Name ASIZE STAY1 STAY2 STAY3 STAY4 AYBURST ACBBURST ACRBURST BSIZE STBY1 STBY2 STBY3 STBY4 BYBURST BCBBURST BCRBURST ADISTWIDTH BDISTWIDTH YRATIO CRATIO YORIGINAL CORIGINAL STACB1 STACB2 STACB3 STACB4 Address (B. Endian) 0x4F000000 0x4F000004 0x4F000008 0x4F00000C 0x4F000010 0x4F000014 0x4F000018 0x4F00001C 0x4F000020 0x4F000024 0x4F000028 0x4F00002C 0x4F000030 0x4F000034 0x4F000038 0x4F00003C 0x4F000040 0x4F000044 0x4F00004C 0x4F000050 0x4F000054 0x4F00005C 0x4F000074 0x4F000078 0x4F00007C 0x4F000080 W Address (L. Endian)
Acc. Unit W
Read/ Write W R/W A-port Image Size
Function
Camera Interface Y start address for 1 ping-pong memory of Aport Image Y start address for 2 port Image
nd st
ping-pong memory of A-
Y start address for 3 ping-pong memory of Aport Image Y start address for 4 ping-pong memory of Aport Image A-port Image Y data burst length A-port Image Cb data burst length A-port Image Cr data burst length B-port Image Size Y start address for 1 ping-pong memory of Bport Image Y start address for 2 port Image
nd st th
rd
ping-pong memory of B-
Y start address for 3 ping-pong memory of Bport Image Y start address for 4 ping-pong memory of Bport Image B-port Image Y data burst length B-port Image Cb data burst length B-port Image Cr data burst length A Last HREF Distance Width B Last HREF Distance Width Y Scale Ratio C Scale Ratio Y Original Size C Original Size A Cb 1 Start Address A Cb 2 Start Address A Cb 3 Start Address A Cb 4 Start Address
th
rd
1-32
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X
PRODUCT OVERVIEW
Table 1-4. S3C2440X Special Registers (Sheet 7 of 14) Register Name STACR1 STACR2 STACR3 STACR4 STBCB1 STBCB2 STBCB3 STBCB4 STBCR1 STBCR2 STBCR3 STBCR4 CTRL RDSTAT RDSTAY RDSTACB RDSTACR RDSTACB1 RDSTACR1 RDSTBY1 RDSTBY2 RDSTBY3 RDSTBY4 RDSTBY RDSTBCB RDSTBCR RDSTBCB1 RDSTBCR1 RDADISTWIDTH RDBDISTWIDTH Address (B. Endian) 0x4F000084 0x4F000088 0x4F00008C 0x4F000090 0x4F00009C 0x4F0000A0 0x4F0000A4 0x4F0000A8 0x4F0000AC 0x4F0000B0 0x4F0000B4 0x4F0000B8 0x4F0000BC 0x4F000000 0x4F000014 0x4F000018 0x4F00001C 0x4F000020 0x4F000024 0x4F000028 0x4F00002C 0x4F000030 0x4F000034 0x4F000038 0x4F00003C 0x4F000040 0x4F000044 0x4F000048 0x4F00004C 0x4F000050 R Address (L. Endian)
Acc. Unit W
Read/ Write W
Function
Camera Interface(Continued) A Cr 1 Start Address A Cr 2 Start Address A Cr 3 Start Address A Cr 4 Start Address B Cb 1 Start Address B Cb 2 Start Address B Cb 3 Start Address B Cb 4 Start Address B Cr 1 Start Address B Cr 2 Start Address B Cr 3 Start Address B Cr 4 Start Address Control Register Status Read Register A Y Start Address Read A Cb Start Address Read A Cr Start Address Read A Cb1 Start Address Read A Cr1 Start Address Read B Y1 Start Address Read B Y2 Start Address Read B Y3 Start Address Read B Y4 Start Address Read B Y Start Address Read B Cb Start Address Read B Cr Start Address Read B Cb1 Start Address Read B Cr1 Start Address Read A Last HREF Distance Width B Last HREF Distance Width
1-33
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
PRODUCT OVERVIEW
S3C2440X
Table 1-4. S3C2440X Special Registers (Sheet 8 of 14) Register Name UART ULCON0 UCON0 UFCON0 UMCON0 UTRSTAT0 UERSTAT0 UFSTAT0 UMSTAT0 UTXH0 URXH0 UBRDIV0 ULCON1 UCON1 UFCON1 UMCON1 UTRSTAT1 UERSTAT1 UFSTAT1 UMSTAT1 UTXH1 URXH1 UBRDIV1 ULCON2 UCON2 UFCON2 UTRSTAT2 UERSTAT2 UFSTAT2 UTXH2 URXH2 UBRDIV2 0x50000000 0x50000004 0x50000008 0x5000000C 0x50000010 0x50000014 0x50000018 0x5000001C 0x50000023 0x50000027 0x50000028 0x50004000 0x50004004 0x50004008 0x5000400C 0x50004010 0x50004014 0x50004018 0x5000401C 0x50004023 0x50004027 0x50004028 0x50008000 0x50008004 0x50008008 0x50008010 0x50008014 0x50008018 0x50008023 0x50008027 0x50008028 0x50008020 0x50008024

Address (B. Endian)
Address (L. Endian)
Acc. Unit W
Read/ Write R/W
Function
UART 0 Line Control UART 0 Control UART 0 FIFO Control UART 0 Modem Control
R
UART 0 Tx/Rx Status UART 0 Rx Error Status UART 0 FIFO Status UART 0 Modem Status
0x50000020 0x50000024
B W
W R R/W
UART 0 Transmission Hold UART 0 Receive Buffer UART 0 Baud Rate Divisor UART 1 Line Control UART 1 Control UART 1 FIFO Control UART 1 Modem Control
R
UART 1 Tx/Rx Status UART 1 Rx Error Status UART 1 FIFO Status UART 1 Modem Status
0x50004020 0x50004024
B W
W R R/W
UART 1 Transmission Hold UART 1 Receive Buffer UART 1 Baud Rate Divisor UART 2 Line Control UART 2 Control UART 2 FIFO Control
R
UART 2 Tx/Rx Status UART 2 Rx Error Status UART 2 FIFO Status
B W
W R R/W
UART 2 Transmission Hold UART 2 Receive Buffer UART 2 Baud Rate Divisor
1-34
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X
PRODUCT OVERVIEW
Table 1-4. S3C2440X Special Registers (Sheet 9 of 14) Register Name PWM Timer TCFG0 TCFG1 TCON TCNTB0 TCMPB0 TCNTO0 TCNTB1 TCMPB1 TCNTO1 TCNTB2 TCMPB2 TCNTO2 TCNTB3 TCMPB3 TCNTO3 TCNTB4 TCNTO4 0x51000000 0x51000004 0x51000008 0x5100000C 0x51000010 0x51000014 0x51000018 0x5100001C 0x51000020 0x51000024 0x51000028 0x5100002C 0x51000030 0x51000034 0x51000038 0x5100003C 0x51000040 R R/W R R R/W R R/W R R/W
Address (B. Endian)
Address (L. Endian)
Acc. Unit W
Read/ Write R/W
Function
Timer Configuration Timer Configuration Timer Control Timer Count Buffer 0 Timer Compare Buffer 0 Timer Count Observation 0 Timer Count Buffer 1 Timer Compare Buffer 1 Timer Count Observation 1 Timer Count Buffer 2 Timer Compare Buffer 2 Timer Count Observation 2 Timer Count Buffer 3 Timer Compare Buffer 3 Timer Count Observation 3 Timer Count Buffer 4 Timer Count Observation 4
1-35
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
PRODUCT OVERVIEW
S3C2440X
Table 1-4. S3C2440X Special Registers (Sheet 10 of 14)) Register Name USB Device FUNC_ADDR_REG PWR_REG EP_INT_REG USB_INT_REG EP_INT_EN_REG USB_INT_EN_REG FRAME_NUM1_REG FRAME_NUM2_REG INDEX_REG EP0_CSR IN_CSR1_REG IN_CSR2_REG MAXP_REG OUT_CSR1_REG OUT_CSR2_REG OUT_FIFO_CNT1_REG OUT_FIFO_CNT2_REG EP0_FIFO EP1_FIFO EP2_FIFO EP3_FIFO EP4_FIFO EP1_DMA_CON EP1_DMA_UNIT EP1_DMA_FIFO EP1_DMA_TTC_L EP1_DMA_TTC_M EP1_DMA_TTC_H 0x52000143 0x52000147 0x5200014B 0x5200015B 0x5200015F 0x5200016F 0x52000173 0x52000177 0x5200017B 0x52000187 0x52000187 0x5200018B 0x52000183 0x52000193 0x52000197 0x5200019B 0x5200019F 0x520001C3 0x520001C7 0x520001CB 0x520001CF 0x520001D3 0x52000203 0x52000207 0x5200020B 0x5200020F 0x52000213 0x52000217 0x52000140 0x52000144 0x52000148 0x52000158 0x5200015C 0x5200016C 0x52000170 0x52000174 0x52000178 0x52000184 0x52000184 0x52000188 0x52000180 0x52000190 0x52000194 0x52000198 0x5200019C 0x520001C0 0x520001C4 0x520001C8 0x520001CC 0x520001D0 0x52000200 0x52000204 0x52000208 0x5200020C 0x52000210 0x52000214 R/W R R/W R B R/W Function Address Power Management EP Interrupt Pending and Clear USB Interrupt Pending and Clear Interrupt Enable Interrupt Enable Frame Number Lower Byte Frame Number Higher Byte Register Index Endpoint 0 Status In Endpoint Control Status In Endpoint Control Status Endpoint Max Packet Out Endpoint Control Status Out Endpoint Control Status Endpoint Out Write Count Endpoint Out Write Count Endpoint 0 FIFO Endpoint 1 FIFO Endpoint 2 FIFO Endpoint 3 FIFO Endpoint 4 FIFO EP1 DMA Interface Control EP1 DMA Tx Unit Counter EP1 DMA Tx FIFO Counter EP1 DMA Total Tx Counter EP1 DMA Total Tx Counter EP1 DMA Total Tx Counter Address (B. Endian) Address (L. Endian) Acc. Unit Read/W rite Function
1-36
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X
PRODUCT OVERVIEW
Table 1-4. S3C2440X Special Registers (Sheet 11 of 14) Register Name USB Device (Continued) EP2_DMA_CON EP2_DMA_UNIT EP2_DMA_FIFO EP2_DMA_TTC_L EP2_DMA_TTC_M EP2_DMA_TTC_H EP3_DMA_CON EP3_DMA_UNIT EP3_DMA_FIFO EP3_DMA_TTC_L EP3_DMA_TTC_M EP3_DMA_TTC_H EP4_DMA_CON EP4_DMA_UNIT EP4_DMA_FIFO EP4_DMA_TTC_L EP4_DMA_TTC_M EP4_DMA_TTC_H Watchdog Timer WTCON WTDAT WTCNT IIC IICCON IICSTAT IICADD IICDS IICLC IIS IISCON IISMOD IISPSR IISFCON IISFIFO 0x55000000,02 0x55000004,06 0x55000000 0x55000004 HW,W R/W IIS Control IIS Mode IIS Prescaler IIS FIFO Control HW IIS FIFO Entry 0x54000000 0x54000004 0x54000008 0x5400000C 0x54000010
Address (B. Endian) 0x5200021B 0x5200021F 0x52000223 0x52000227 0x5200022B 0x5200022F 0x52000243 0x52000247 0x5200024B 0x5200024F 0x52000253 0x52000257 0x5200025B 0x5200025F 0x52000263 0x52000267 0x5200026B 0x5200026F 0x53000000 0x53000004 0x53000008
Address (L. Endian) 0x52000218 0x5200021C 0x52000220 0x52000224 0x52000228 0x5200022C 0x52000240 0x52000244 0x52000248 0x5200024C 0x52000250 0x52000254 0x52000258 0x5200025C 0x52000260 0x52000264 0x52000268 0x5200026C
Acc. Unit B
Read/W rite R/W
Function
EP2 DMA Interface Control EP2 DMA Tx Unit Counter EP2 DMA Tx FIFO Counter EP2 DMA Total Tx Counter EP2 DMA Total Tx Counter EP2 DMA Total Tx Counter EP3 DMA Interface Control EP3 DMA Tx Unit Counter EP3 DMA Tx FIFO Counter EP3 DMA Total Tx Counter EP3 DMA Total Tx Counter EP3 DMA Total Tx Counter EP4 DMA Interface Control EP4 DMA Tx Unit Counter EP4 DMA Tx FIFO Counter EP4 DMA Total Tx Counter EP4 DMA Total Tx Counter EP4 DMA Total Tx Counter
W
R/W
Watchdog Timer Mode Watchdog Timer Data Watchdog Timer Count
W
R/W
IIC Control IIC Status IIC Address IIC Data Shift IIC multi-master line control
0x55000008,0A 0x55000008 0x5500000C,0E 0x5500000C 0x55000012 0x55000010
1-37
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
PRODUCT OVERVIEW
S3C2440X
Table 1-4. S3C2440X Special Registers (Sheet 12 of 14) Register Name I/O port GPACON GPADAT GPBCON GPBDAT GPBUP GPCCON GPCDAT GPCUP GPDCON GPDDA1T GPDUP GPECON GPEDAT GPEUP GPFCON GPFDAT GPFUP GPGCON GPGDAT GPGUP GPHCON GPHDAT GPHUP GPJCON GPJDAT GPJUP MISCCR DCLKCON EXTINT0 EXTINT1 EXTINT2 0x56000000 0x56000004 0x56000010 0x56000014 0x56000018 0x56000020 0x56000024 0x56000028 0x56000030 0x56000034 0x56000038 0x56000040 0x56000044 0x56000048 0x56000050 0x56000054 0x56000058 0x56000060 0x56000064 0x56000068 0x56000070 0x56000074 0x56000078 0x560000D0 0x560000D4 0x560000D8 0x56000080 0x56000084 0x56000088 0x5600008C 0x56000090
Address (B. Endian)
Address (L. Endian)
Acc. Unit
Read/ Write
Function
W
R/W
Port A Control Port A Data Port B Control Port B Data Pull-up Control B Port C Control Port C Data Pull-up Control C Port D Control Port D Data Pull-up Control D Port E Control Port E Data Pull-up Control E Port F Control Port F Data Pull-up Control F Port G Control Port G Data Pull-up Control G Port H Control Port H Data Pull-up Control H Port J Control Port J Data Pull-up Control J Miscellaneous Control DCLK0/1 Control External Interrupt Control Register 0 External Interrupt Control Register 1 External Interrupt Control Register 2
1-38
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X
PRODUCT OVERVIEW
Table 1-4. S3C2440X Special Registers (Sheet 13 of 14) Register Name EINTFLT0 EINTFLT1 EINTFLT2 EINTFLT3 EINTMASK EINTPEND GSTATUS0 GSTATUS1 GSTATUS2 GSTATUS3 GSTATUS4 MSLCON RTC RTCCON TICNT RTCALM ALMSEC ALMMIN ALMHOUR ALMDATE ALMMON ALMYEAR RTCRST BCDSEC BCDMIN BCDHOUR BCDDATE BCDDAY BCDMON BCDYEAR 0x57000043 0x57000047 0x57000053 0x57000057 0x5700005B 0x5700005F 0x57000063 0x57000067 0x5700006B 0x5700006F 0x57000073 0x57000077 0x5700007B 0x5700007F 0x57000083 0x57000087 0x5700008B 0x57000040 0x57000044 0x57000050 0x57000054 0x57000058 0x5700005C 0x57000060 0x57000064 0x57000068 0x5700006C 0x57000070 0x57000074 0x57000078 0x5700007C 0x57000080 0x57000084 0x57000088 B R/W RTC Control Tick time count RTC Alarm Control Alarm Second Alarm Minute Alarm Hour Alarm Day Alarm Month Alarm Year RTC Round Reset BCD Second BCD Minute BCD Hour BCD Day BCD Date BCD Month BCD Year Address (B. Endian) 0x56000094 0x56000098 0x5600009C 0x560000A0 0x560000A4 0x560000A8 0x560000AC 0x560000B0 0x560000B4 0x560000B8 0x560000BC 0x560000CC R R/W Address (L. Endian)
Acc. Unit W
Read/ Write R/W Reserved Reserved
Function
I/O port (Continued)
External Interrupt Filter Control Register 2 External Interrupt Filter Control Register 3 External Interrupt Mask External Interrupt Pending External Pin Status Chip ID Reset Status Inform Register Inform Register Memory Sleep Control Register
1-39
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
PRODUCT OVERVIEW
S3C2440X
Table 1-4. S3C2440X Special Registers (Sheet 14 of 14) Register Name A/D converter ADCCON ADCTSC ADCDLY ADCDAT0 ADCDAT1 ADCUPDN SPI SPCON0,1 SPSTA0,1 SPPIN0,1 SPPRE0,1 SPTDAT0,1 SPRDAT0,1 SD interface SDICON SDIPRE SDICARG SDICCON SDICSTA SDIRSP0 SDIRSP1 SDIRSP2 SDIRSP3 SDIDTIMER SDIBSIZE SDIDCON SDIDCNT SDIDSTA SDIFSTA SDIDAT SDIIMSK 0x5A000000 0x5A000004 0x5A000008 0x5A00000C 0x5A000010 0x5A000014 0x5A000018 0x5A00001C 0x5A000020 0x5A000024 0x5A000028 0x5A00002C 0x5A000030 0x5A000034 0x5A000038 0x5A00003F 0x5A000040 0x5A00003C

Address (B. Endian) 0x58000000 0x58000004 0x58000008 0x5800000C 0x58000010 0x58000014 0x59000000,20 0x59000004,24 0x59000008,28 0x5900000C,2C 0x59000010,30 0x59000014,34
Address (L. Endian)
Acc. Unit
Read/ Write R/W ADC Control
Function
W
ADC Touch Screen Control ADC Start or Interval Delay R R/W
ADC Conversion Data ADC Conversion Data Stylus Up or Down Interrpt status SPI Control SPI Status SPI Pin Control SPI Baud Rate Prescaler SPI Tx Data
W
R/W R R/W
R W R/W
SPI Rx Data SDI Control SDI Baud Rate Prescaler SDI Command Argument SDI Command Control
R/(C) R
SDI Command Status SDI Response SDI Response SDI Response SDI Response
R/W
SDI Data / Busy Timer SDI Block Size SDI Data control
R R/(C) R B W R/W
SDI Data Remain Counter SDI Data Status SDI FIFO Status SDI Data SDI Interrupt Mask
1-40
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
PRODUCT OVERVIEW
S3C2440X
Table 1-4. S3C2440X Special Registers (Sheet of 14 of 14) Register Name A/D converter ADCCON ADCTSC ADCDLY ADCDAT0 ADCDAT1 ADCUPDN SPI SPCON0,1 SPSTA0,1 SPPIN0,1 SPPRE0,1 SPTDAT0,1 SPRDAT0,1 SD interface SDICON SDIPRE SDICARG SDICCON SDICSTA SDIRSP0 SDIRSP1 SDIRSP2 SDIRSP3 SDIDTIMER SDIBSIZE SDIDCON SDIDCNT SDIDSTA SDIFSTA SDIDAT SDIIMSK 0x5A000000 0x5A000004 0x5A000008 0x5A00000C 0x5A000010 0x5A000014 0x5A000018 0x5A00001C 0x5A000020 0x5A000024 0x5A000028 0x5A00002C 0x5A000030 0x5A000034 0x5A000038 0x5A00003F 0x5A000040 0x5A00003C

Address (B. Endian) 0x58000000 0x58000004 0x58000008 0x5800000C 0x58000010 0x58000014 0x59000000,20 0x59000004,24 0x59000008,28 0x5900000C,2C 0x59000010,30 0x59000014,34
Address (L. Endian)
Acc. Unit
Read/ Write R/W ADC Control
Function
W
ADC Touch Screen Control ADC Start or Interval Delay R R/W
ADC Conversion Data ADC Conversion Data Stylus Up or Down Interrpt status SPI Control SPI Status SPI Pin Control SPI Baud Rate Prescaler SPI Tx Data
W
R/W R R/W
R W R/W
SPI Rx Data SDI Control SDI Baud Rate Prescaler SDI Command Argument SDI Command Control
R/(C) R
SDI Command Status SDI Response SDI Response SDI Response SDI Response
R/W
SDI Data / Busy Timer SDI Block Size SDI Data control
R R/(C) R B W R/W
SDI Data Remain Counter SDI Data Status SDI FIFO Status SDI Data SDI Interrupt Mask
1-40
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
MEMORY CONTROLLER
5
MEMORY CONTROLLER
OVERVIEW
The S3C2440X memory controller provides memory control signals that are required for external memory access. The S3C2440X has the following features: -- Little/Big endian (selectable by a software) -- Address space: 128Mbytes per bank (total 1GB/8 banks) -- Programmable access size (8/16/32-bit) for all banks except bank0 (16/32-bit) -- Total 8 memory banks Six memory banks for ROM, SRAM, etc. Remaining two memory banks for ROM, SRAM, SDRAM, etc . -- Seven fixed memory bank start address -- One flexible memory bank start address and programmable bank size -- Programmable access cycles for all memory banks -- External wait to extend the bus cycles -- Supporting self-refresh and power down mode in SDRAM
5-1
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
MEMORY CONTROLLER
S3C2440X RISC MICROPROCESSOR
0x40000_0000
OM[1:0] = 01,10 SROM/SDRAM (nGCS7)
OM[1:0] = 00 SROM/SDRAM (nGCS7)
2MB/4MB/8MB/16MB /32MB/64MB/128MB Refer to Table 5-1
0x3800_0000
}
SROM/SDRAM (nGCS6)
0x3000_0000
SROM/SDRAM (nGCS6)
2MB/4MB/8MB/16MB /32MB/64MB/128MB
SROM (nGCS5)
0x2800_0000
SROM (nGCS5)
128MB
SROM (nGCS4)
0x2000_0000
SROM (nGCS4)
128MB
SROM (nGCS3)
0x1800_0000
SROM (nGCS3)
1GB HADDR[29:0] Accessible Region
128MB
SROM (nGCS2)
0x1000_0000
SROM (nGCS2)
128MB
SROM (nGCS1)
0x0800_0000
SROM (nGCS1)
128MB
SROM (nGCS0)
0x0000_0000
Boot Internal SRAM (4KB)
128MB
[ Not using NAND flash for boot ROM ]
[ Using NAND flash for boot ROM ]
Note: SROM means ROM or SRAM type memory
Figure 5-1. S3C2440X Memory Map after Reset
Table 5-1. Bank 6/7 Addresses Address 2MB 4MB 8MB Bank 6 Start address 0x3000_0000 End address 0x301F_FFFF Start address 0x3020_0000 End address 0X303F_FFFF
0x3000_0000 0X303F_FFFF 0x3000_0000 0X307F_FFFF 0x3000_0000 0X30FF_FFFF 0x3000_0000 0X31FF_FFFF 0x3000_0000 0X33FF_FFFF 0x3000_0000 0X37FF_FFFF
16MB
32MB
64MB
128MB
Bank 7
0x3040_0000 0X307F_FFFF 0x3080_0000 0X30FF_FFFF 0x3100_0000 0X31FF_FFFF 0x3200_0000 0X33FF_FFFF 0x3400_0000 0X37FF_FFFF 0x3800_0000 0X3FFF_FFFF
Note: Bank 6 and 7 must have the same memory size.
5-2
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
MEMORY CONTROLLER
DEC.13, 2002
FUNCTION DESCRIPTION
BANK0 BUS WIDTH The data bus of BANK0 (nGCS0) should be configured in width as one of 16-bit and 32-bit ones. Because the BANK0 works as the booting ROM bank (map to 0x0000_0000), the bus width of BANK0 should be determined before the first ROM access, which will depend on the logic level of OM[1:0] at Reset. OM1 (Operating Mode 1) 0 0 1 1 OM0 (Operating Mode 0) 0 1 0 1 Booting ROM Data width Nand Flash Mode 16-bit 32-bit Test Mode
MEMORY (SROM/SDRAM) ADDRESS PIN CONNECTIONS MEMORY ADDR. PIN A0 A1 ... S3C2440X ADDR.
@ 8-bit DATA BUS
S3C2440X ADDR.
@ 16-bit DATA BUS
S3C2440X ADDR.
@ 32-bit DATA BUS
A0 A1 ...
A1 A2 ...
A2 A3 ...
5-3
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
MEMORY CONTROLLER
S3C2440X RISC MICROPROCESSOR
SDRAM BANK ADDRESS PIN CONNECTION EXAMPLE Table 5-2. SDRAM Bank Address Configuration Bank Size
2MByte
Bus Width
x8 x16
Base Component
16Mbit
Memory Configuration
(1M x 8 x 2Bank) x 1 (512K x 16 x 2B) x 1 (1M x 8 x 2B) x 2 (1M x 8 x 2B) x 2
Bank Address
A20
4MB
x16 x16
A21
8MB
x16 x32 x8 x8 x16 x16 x32
16Mb
(2M x 4 x 2B) x 4 (1M x 8x 2B) x 4
A22
64Mb
(4M x 8 x 2B) x 1 (2M x 8 x 4B) x 1 (2M x 16 x 2B) x 1 (1M x 16 x 4B) x 1 (512K x 32 x 4B) x 1 A[22:21] A22 A[22:21]
16MB
x32 x8 x8 x16 x16 x32 x32 x8 x16
16Mb 64Mb
(2M x 4 x 2B) x 8 (8M x 4 x 2B) x 2 (4M x 4 x 4B) x 2 (4M x 8 x 2B) x 2 (2M x 8 x 4B) x 2 (2M x 16 x 2B) x 2 (1M x 16 x 4B) x 2
A23
A[23:22] A23 A[23:22] A23 A[23:22]
128Mb
(4M x 8 x 4B) x 1 (2M x 16 x 4B) x 1
32MB
x16 x16 x32 x32 x16 x32 x8 x16
64Mb
(8M x 4 x 2B) x 4 (4M x 4 x 4B) x 4 (4M x 8 x 2B) x 4 (2M x 8 x 4B) x 4
A24 A[24:23] A24 A[24:23]
128Mb
(4M x 8 x 4B) x 2 (2M x 16 x 4B) x 2
256Mb
(8M x 8 x 4B) x 1 (4M x 16 x 4B) x 1
64MB
x32 x16 x32 x8
128Mb 256Mb
(4M x 8 x 4B) x 4 (8M x 8 x 4B) x 2 (4M x 16 x 4B) x 2
A[25:24]
512Mb 256Mbit 512Mb
(16M x 8 x 4B) x 1 (8M x 8 x 4Bank) x 4 (32M x 4 x 4B) x 2 (16M x 8 x 4B) x 2 (8M x 16 x 4B) x 2 A[26:25]
128MB
x32 x8 x16 x32
5-4
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
MEMORY CONTROLLER
DEC.13, 2002 nWAIT PIN OPERATION If the WAIT corresponding to each memory bank is enabled, the nOE duration should be prolonged by the external nWAIT pin while the memory bank is active. nWAIT is checked from tacc-1. nOE will be deasserted at the next clock after sampling nWAIT is high. The nWE signal have the same relation with nOE.
HCLK tRC ADDR
nGCS
Tacs Tacc=4 Tcos Sampling nWAIT Delayed
nOE
nWAIT DATA(R)
Figure 5-2. S3C2440X External nWAIT Timing Diagram (Tacc=4)
5-5
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
MEMORY CONTROLLER
S3C2440X RISC MICROPROCESSOR
nXBREQ/nXBACK Pin Operation If nXBREQ is asserted, the S3C2440X will respond by lowering nXBACK. If nXBACK=L, the address/data bus and memory control signals are in Hi-Z state as shown in Table 1-1. When nXBREQ is de-asserted, the nXBACK will also be de-asserted.
HCLK
SCLK SCKE, A[24:0] D[31:0], nGCS nOE,nWE nWBE nXBREQ 1clk
nXBACK
Figure 5-3. S3C2440X nXBREQ/nXBACK Timing Diagram
5-6
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
MEMORY CONTROLLER
DEC.13, 2002 ROM Memory Interface Examples
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE
D0 D1 D2 D3 D4 D5 D6 D7 nWE nOE nGCSn
Figure 5-4. Memory Interface with 8-bit ROM
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE
D0 D1 D2 D3 D4 D5 D6 D7 nWBE0 nOE nGCSn
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE
D8 D9 D10 D11 D12 D13 D14 D15 nWBE1 nOE nGCSn
Figure 5-5. Memory Interface with 8-bit ROM x 2
5-7
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
MEMORY CONTROLLER
S3C2440X RISC MICROPROCESSOR
A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE
D0 D1 D2 D3 D4 D5 D6 D7
A2 A3 A4 A5 A6 A7 A8 A9 A10 nWBE0 A11 nOE A12 nGCSn A13 A14 A15 A16 A17
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE
D8 D9 D10 D11 D12 D13 D14 D15
A2 A3 A4 A5 A6 A7 A8 A9 A10 nWBE1 A11 nOE A12 nGCSn A13 A14 A15 A16 A17
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE
D16 D17 D18 D19 D20 D21 D22 D23
A2 A3 A4 A5 A6 A7 A8 A9 A10 nWBE2 A11 nOE A12 nGCSn A13 A14 A15 A16 A17
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE
D24 D25 D26 D27 D28 D29 D30 D31 nWBE3 nOE nGCSn
Figure 5-6. Memory Interface with 8-bit ROM x 4
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nWE nOE nCE
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 nWE nOE nGCSn
Figure 5-7. Memory Interface with 16-bit ROM
5-8
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
MEMORY CONTROLLER
DEC.13, 2002 SRAM Memory Interface Examples
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nWE nOE nCS nUB nLB
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 nWE nOE nGCSn nBE1 nBE0
Figure 5-8. Memory Interface with 16-bit SRAM
A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nWE nOE nCS nUB nLB
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 nWE nOE nGCSn nBE1 nBE0
A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nWE nOE nCS nUB nLB
D16 D17 D18 D19 D20 D21 D22 D13 D24 D25 D26 D27 D28 D29 D30 D31 nWE nOE nGCSn nBE3 nBE2
Figure 5-9. Memory Interface with 16-bit SRAM x 2
5-9
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
MEMORY CONTROLLER
S3C2440X RISC MICROPROCESSOR
SDRAM Memory Interface Examples
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A21 A22 DQM0 DQM1 SCKE SCLK
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 LDQM UDQM SCKE SCLK
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nSCS nSRAS nSCAS nWE
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 nSCS0 nSRAS nSCAS nWE
Figure 5-10. Memory Interface with 16-bit SDRAM (4Mx16, 4banks)
A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A22 A23 DQM0 DQM1 SCKE SCLK
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 LDQM UDQM SCKE SCLK
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nSCS nSRAS nSCAS nWE
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 nSCS0 nSRAS nSCAS nWE
A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A22 A23 DQM2 DQM3 SCKE SCLK
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 LDQM UDQM SCKE SCLK
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nSCS nSRAS nSCAS nWE
D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 nSCS0 nSRAS nSCAS nWE
Figure 5-11. Memory Interface with 16-bit SDRAM (4Mx16 * 2ea, 4banks)
Note: Refer to Table 5-2 for the Bank Address configurations of SDRAM.
5-10
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
MEMORY CONTROLLER
DEC.13, 2002 PROGRAMMABLE ACCESS CYCLE
HCLK
A[24:0]
nGCS
Tacs Tcos Tacc Tacp Tcoh
Tcah
nOE
nWE
nWBE
D[31:0](R)
D[31:0] (W)
Tacs = 1 cycle Tcos = 1 cycle Tacc = 3 cycles
Tacp = 2 cycles Tcoh = 1 cycle Tcah = 2 cycles
Figure 5-12. S3C2440X nGCS Timing Diagram
5-11
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
MEMORY CONTROLLER
S3C2440X RISC MICROPROCESSOR
MCLK SCKE nSCS Trp
nSRAS
nSCAS
Trcd
ADDR
RA
Ca
Cb
Cc
Cd
Ce
BA
BA
BA
BA
BA
BA
BA
BA
A10/AP
RA
DATA (CL2)
Da
Db
Dc
Dd
De
DATA (CL3)
Da
Db
Dc
Dd
De
nWE
DQM
Bank Precharge
Row Active
Write
Read (CL = 2, CL = 3, BL = 1)
Trp = 2 cycle Trcd = 2 cycle
Tcas = 2 cycle Tcp = 2 cycle
Figure 5-13. S3C2440X SDRAM Timing Diagram
5-12
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
MEMORY CONTROLLER
DEC.13, 2002 BUS WIDTH & WAIT CONTROL REGISTER (BWSCON) Register BWSCON Address 0x48000000 R/W R/W Description Bus width & wait status control register Reset Value 0x000000
BWSCON ST7
Bit [31]
Description Determine SRAM for using UB/LB for bank 7. 0 = Not using UB/LB (The pins are dedicated nWBE[3:0]) 1 = Using UB/LB (The pins are dedicated nBE[3:0]) Determine WAIT status for bank 7. 0 = WAIT disable 1 = WAIT enable Determine data bus width for bank 7. 00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = reserved
Initial state 0
WS7 DW7 ST6
[30] [29:28] [27]
0 0 0
Determine SRAM for using UB/LB for bank 6. 0 = Not using UB/LB (The pins are dedicated nWBE[3:0 ) 1 = Using UB/LB (The pins are dedicated nBE[3:0]) Determine WAIT status for bank 6. 0 = WAIT disable, 1 = WAIT enable Determine data bus width for bank 6. 00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = reserved
WS6 DW6 ST5
[26] [25:24] [23]
0 0 0
Determine SRAM for using UB/LB for bank 5. 0 = Not using UB/LB (The pins are dedicated nWBE[3:0]) 1 = Using UB/LB (The pins are dedicated nBE[3:0]) Determine WAIT status for bank 5. 0 = WAIT disable, 1 = WAIT enable Determine data bus width for bank 5. 00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = reserved
WS5 DW5 ST4
[22] [21:20] [19]
0 0 0
Determine SRAM for using UB/LB for bank 4. 0 = Not using UB/LB (The pins are dedicated nWBE[3:0]) 1 = Using UB/LB (The pins are dedicated nBE[3:0]) Determine WAIT status for bank 4. 0 = WAIT disable 1 = WAIT enable Determine data bus width for bank 4. 00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = reserved
WS4 DW4 ST3
[18] [17:16] [15]
0 0 0
Determine SRAM for using UB/LB for bank 3. 0 = Not using UB/LB (The pins are dedicated nWBE[3:0]) 1 = Using UB/LB (The pins are dedicated nBE[3:0]) Determine WAIT status for bank 3. 0 = WAIT disable 1 = WAIT enable Determine data bus width for bank 3. 00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = reserved
WS3 DW3 ST2
[14] [13:12] [11]
0 0 0
Determine SRAM for using UB/LB for bank 2. 0 = Not using UB/LB (The pins are dedicated nWBE[3:0]) 1 = Using UB/LB (The pins are dedicated nBE[3:0].)
5-13
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
MEMORY CONTROLLER
S3C2440X RISC MICROPROCESSOR
BUS WIDTH & WAIT CONTROL REGISTER (BWSCON) (Continued) WS2 DW2 ST1 [10] [9:8] [7] Determine WAIT status for bank 2. 0 = WAIT disable 1 = WAIT enable Determine data bus width for bank 2. 00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = reserved 0 0 0
Determine SRAM for using UB/LB for bank 1. 0 = Not using UB/LB (The pins are dedicated nWBE[3:0]) 1 = Using UB/LB (The pins are dedicated nBE[3:0]) Determine WAIT status for bank 1. 0 = WAIT disable, 1 = WAIT enable Determine data bus width for bank 1. 00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = reserved
WS1 DW1 DW0
[6] [5:4] [2:1]
0 0 -
Indicate data bus width for bank 0 (read only). 01 = 16-bit, 10 = 32-bit The states are selected by OM[1:0] pins Reserve to 0
Reserved
[0]
0
Note: 1. All types of master clock in this memory controller correspond to the bus clock. For example, HCLK in SRAM is the same as the bus clock, and SCLK in SDRAM is also the same as the bus clock. In this chapter (Memory Controller), one clock means one bus clock. 2. nBE[3:0] is the 'AND' signal nWBE[3:0] and nOE.
5-14
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
MEMORY CONTROLLER
DEC.13, 2002 BANK CONTROL REGISTER (BANKCONn: nGCS0-nGCS5) Register BANKCON0 BANKCON1 BANKCON2 BANKCON3 BANKCON4 BANKCON5 Address 0x48000004 0x48000008 0x4800000C 0x48000010 0x48000014 0x48000018 R/W R/W R/W R/W R/W R/W R/W Description Bank 0 control register Bank 1 control register Bank 2 control register Bank 3 control register Bank 4 control register Bank 5 control register Reset Value 0x0700 0x0700 0x0700 0x0700 0x0700 0x0700
BANKCONn Tacs
Bit [14:13]
Description Address set-up time before nGCSn 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks Chip selection set-up time before nOE 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks Access cycle 000 = 1 clock 001 = 2 clocks 010 = 3 clocks 011 = 4 clocks 100 = 6 clocks 101 = 8 clocks 110 = 10 clocks 111 = 14 clocks Note: When nWAIT signal is used, Tacc 4 clocks. Chip selection hold time after nOE 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks Address hold time after nGCSn 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks Page mode access cycle @ Page mode 00 = 2 clocks 01 = 3 clocks 10 = 4 clocks 11 = 6 clocks Page mode configuration 00 = normal (1 data) 01 = 4 data 10 = 8 data 11 = 16 data
Initial State 00
Tcos
[12:11]
00
Tacc
[10:8]
111
Tcoh
[7:6]
000
Tcah
[5:4]
00
Tacp
[3:2]
00
PMC
[1:0]
00
5-15
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
MEMORY CONTROLLER
S3C2440X RISC MICROPROCESSOR
BANK CONTROL REGISTER (BANKCONn: nGCS6-nGCS7) Register BANKCON6 BANKCON7 Address 0x4800001C 0x48000020 R/W R/W R/W Description Bank 6 control register Bank 7 control register Reset Value 0x18008 0x18008
BANKCONn MT
Bit [16:15]
Description Determine the memory type for bank6 and bank7. 00 = ROM or SRAM 01 = Reserved (Do not use) 10 = Reserved (Do not use) 11 = Sync. DRAM Address set-up time before nGCS 00 = 0 clock 01 = 1 clock 10 = 2 clocks Chip selection set-up time before nOE 00 = 0 clock 01 = 1 clock 10 = 2 clocks Access cycle 000 = 1 clock 010 = 3 clocks 100 = 6 clocks 110 = 10 clocks 001 = 2 clocks 011 = 4 clocks 101 = 8 clocks 111 = 14 clocks
Initial State 11
Memory Type = ROM or SRAM [MT=00] (15-bit) Tacs Tcos Tacc [14:13] [12:11] [10:8] 00 11 = 4 clocks 00 11 = 4 clocks 111
Toch
[7:6]
Chip selection hold time after nOE 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks Address hold time after nGCSn 00 = 0 clock 01 = 1clock 10 = 2 clocks Page mode access cycle @ Page mode 00 = 2 clocks 01 = 3 clocks 10 = 4 clocks 11 = 6 clocks Page mode configuration 00 = normal (1 data) 10 = 8 consecutive accesses RAS to CAS delay 00 = 2 clocks 01 = 3 clocks Column address number 00 = 8-bit 01 = 9-bit 01 = 4 consecutive accesses 11 = 16 consecutive accesses 11 = 4 clocks
00
Tcah Tacp
[5:4] [3:2]
00 00
PMC
[1:0]
00
Memory Type = SDRAM [MT=11] (4-bit) Trcd SCAN [3:2] [1:0] 10 10 = 4 clocks 00 10= 10-bit
5-16
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
MEMORY CONTROLLER
DEC.13, 2002 REFRESH CONTROL REGISTER Register REFRESH Address 0x48000024 R/W R/W Description SDRAM refresh control register Reset Value 0xac0000
REFRESH REFEN TREFMD
Bit [23] [22] SDRAM Refresh Enable 0 = Disable
Description 1 = Enable (self or CBR/auto refresh)
Initial State 1 0
SDRAM Refresh Mode 0 = CBR/Auto Refresh 1 = Self Refresh In self-refresh time, the SDRAM control signals are driven to the appropriate level. SDRAM RAS pre-charge Time 00 = 2 clocks 01 = 3 clocks 10 = 4 clocks 11 = Not support
Trp Trc Reserved Reserved Refresh Counter
[21:20] [19:18] [17:16] [15:11] [10:0]
10 11 00 0000 0
SDRAM RC minimum Time 00 = 4 clocks 01 = 5 clocks 10 = 6 clocks 11 = 7 clocks Not used Not used SDRAM refresh count value. Refer to chapter 6 SDRAM refresh controller bus priority section. 11 Refresh period = (2 -refresh_count+1)/HCLK Ex) If refresh period is 7.8 us and HCLK is 100 MHz, the refresh count is as follows: 11 Refresh count = 2 + 1 - 100x7.8 = 1269
5-17
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
MEMORY CONTROLLER
S3C2440X RISC MICROPROCESSOR
BANKSIZE REGISTER Register BANKSIZE Address 0x48000028 R/W R/W Description Flexible bank size register Reset Value 0x0
BANKSIZE BURST_EN
Bit [7]
Description ARM core burst operation enable. 0 = Disable burst operation. 1 = Enable burst operation.
Initial State 0
Reserved SCKE_EN
[6] [5]
Not used SDRAM power down mode enable control by SCKE 0 = SDRAM power down mode disable 1 = SDRAM power down mode enable SCLK is enabled only during SDRAM access cycle for reducing power consumption. When SDRAM is not accessed, SCLK becomes 'L' level. 0 = SCLK is always active. 1 = SCLK is active only during the access (recommended).
0 0
SCLK_EN
[4]
0
Reserved BK76MAP
[3] [2:0]
Not used BANK6/7 memory map 010 = 128MB/128MB 000 = 32M/32M 110 = 8M/8M 100 = 2M/2M 001 = 64MB/64MB 111 = 16M/16M 101 = 4M/4M
0 010
5-18
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
MEMORY CONTROLLER
DEC.13, 2002 SDRAM MODE REGISTER SET REGISTER (MRSR) Register MRSRB6 MRSRB7 Address 0x4800002C 0x48000030 R/W R/W R/W Description Mode register set register bank6 Mode register set register bank7 Reset Value xxx xxx
MRSR Reserved WBL
Bit [11:10] [9] Not used Write burst length 0: Burst (Fixed) 1: Reserved
Description
Initial State x
TM
[8:7]
Test mode 00: Mode register set (Fixed) 01, 10 and 11: Reserved CAS latency 000 = 1 clock, 010 = 2 clocks, Others: reserved Burst type 0: Sequential (Fixed) 1: Reserved Burst length 000: 1 (Fixed) Others: Reserved 011=3 clocks
xx
CL
[6:4]
xxx
BT
[3]
x
BL
[2:0]
xxx
Note: MRSR register must not be reconfigured while the code is running on SDRAM.
Important Note: In Sleep mode, SDRAM has to enter SDRAM self-refresh mode.
5-19
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
MEMORY CONTROLLER
S3C2440X RISC MICROPROCESSOR
NOTES
5-20
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
NAND FLASH CONTROLLER
NAND FLASH CONTORLLER
OVERVIEW In recent times, NOR flash memory gets high in price while an SDRAM and a NAND flash memory get moderate, motivating some users to execute the boot code on a NAND flash and execute the main code on an SDRAM. S3C2440X boot code can be executed on an external NAND flash memory. In order to support NAND flash boot loader, the S3C2440X is equipped with an internal SRAM buffer called `Steppingstone'. When booting, the first 4 KBytes of the NAND flash memory will be loaded into Steppingstone and the boot code loaded into Steppingstone will be executed. Generally, the boot code will copy NAND flash content to SDRAM. Using hardware ECC, the NAND flash data validity will be checked. Upon the completion of the copy, the main program will be executed on the SDRAM.
FEATURES 1) Auto boot: The boot code is transferred into 4-kbytes Steppingstone during reset. After the transfer, the boot code will be executed on the Steppingstone. 2) NAND Flash memory I/F: Support 256Words, 512Bytes, 1KWords and 2KBytes Page. 3) Software mode: User can directly access NAND flash memory, for example this feature can be used in read/erase/program NAND flash memory. 4) Interface: 8 / 16-bit NAND flash memory interface bus. 5) Hardware ECC generation, detection and indication (Software correction). 6) SFR I/F: Support Little Endian Mode, Byte/half word/word access to Data and ECC Data register, and Word access to other registers 7) SteppingStone I/F: Support Little/Big Endian, Byte/half word/word access. 8) The Steppingstone 4-KB internal SRAM buffer can be used for another purpose after NAND flash booting.
6-1
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
NAND FLASH CONTROLLER
S3C2440X RISC MICROPROCESSOR
BLOCK DIAGRAM
nFCE CLE ALE nRE nWE R/nB I/O0 - I/O15
ljj nU zmy SYSTEM BUS j M z t uhuk mshzo p
hoi z pVm
z z j
z z O[ri zyhtP
Figure 6-1 NAND Flash Controller Block Diagram
BOOT LOADER FUNCTION
REGISTERS CORE ACCESS (Boot Code) z z O[ri iP uhuk mshzo j z m y uhuk mshzo t AUTO BOOT
USER ACCESS
Figure 6-2 NAND Flash Controller Boot Loader Block Diagram
During reset, Nand flash controller will get information about connected NAND flash through Pin status(NCON(Adv flash), GPG13(Page size), GPG14(Address cycle), GPG15(Bus width) - refer to PIN CONFIGURATION), After power-on or system reset is occurred, the NAND Flash controller load automatically the 4-KBytes boot loader codes. After loading the boot loader codes, the boot loader code in steppingstone is executed. NOTE : During the auto boot, the ECC is not checked. So, the first 4-KB of NAND flash should have no bit error.
6-2
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
NAND FLASH CONTROLLER
PIN CONFIGURATION OM[1:0] = 00: Enable NAND flash memory boot NCON : NAND flash memory selection(Normal / Advance) 0: Normal NAND flash(256Words/512Bytes page size, 3/4 address cycle) 1: Advance NAND flash(1KWords/2KBytes page size, 4/5 address cycle) GPG13 : NAND flash memory page capacitance selection 0: Page=256Words(NCON = 0) or Page=1KWords(NCON = 1) 1: Page=512Bytes(NCON = 0) or Page=2KBytes(NCON = 1) GPG14: NAND flash memory address cycle selection 0: 3 address cycle(NCON = 0) or 4 address cycle(NCON = 1) 1: 4 address cycle(NCON = 0) or 5 address cycle(NCON = 1) GPG15 : NAND flash memory bus width selection 0: 8-bit bus width 1: 16-bit bus width
NAND FLASH MEMORY CONFIGURATION TABLE NCON0 0: Normal NAND GPG13 0: 256Words 1: 512Bytes 1: Advance NAND 0: 1Kwords GPG14 0: 3-Addr 1: 4-Addr 0: 4-Addr GPG15 0: 8-bit bus width
1: 16-bit bus width 1: 2Kbytes 1: 5-Addr Note: With above 4-bit, Possible total combinations are 16, but not all the value can be used.
Example) Nand flash configuration setting example. Parts K9S1208V0M-xxxx K9K2G16U0M-xxxx Page size/Total size 512Byte / 512Mbit 1KW / 2Gbit NCON0 0 1 GPG13 1 0 GPG14] 1 1 GPG15 0 1
6-3
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
NAND FLASH CONTROLLER
S3C2440X RISC MICROPROCESSOR
NAND FLASH MEMORY TIMING
TACLS TWRPH0 TWRPH1
HCLK
CLE / ALE
nWE
DATA
COMMAND / ADDRESS
Figure 6-3. CLE & ALE Timing (TACLS=1, TWRPH0=0, TWRPH1=0)
TWRPH0
TWRPH1
HCLK
nWE / nRE
DATA
DATA
Figure 6-4 nWE & nRE Timing (TWRPH0=0, TWRPH1=0)
6-4
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
NAND FLASH CONTROLLER
SOFTWARE MODE
S3C2440X only supports software mode access. Using this mode, you can completely access the NAND flash memory. The NAND Flash Controller supports direct access interface with the NAND flash memory. 1) Writing to the command register = the NAND Flash Memory command cycle 2) Writing to the address register = the NAND Flash Memory address cycle 3) Writing to the data register = write data to the NAND Flash Memory (write cycle) 4) Reading from the data register = read data from the NAND Flash Memory (read cycle) 5) Reading main ECC registers and Spare ECC registers = read data from the NAND Flash Memory NOTE : In the software mode, you have to check the RnB status input pin by using polling or interrupt.
6-5
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
NAND FLASH CONTROLLER
S3C2440X RISC MICROPROCESSOR
Data Register Configuration 1) 16-bit NAND Flash Memory Interface A. Word Access Register NFDATA NFDATA Endian Little Big Bit [31:24] 2 I/O[15:8] 1 I/O[15:8]
st nd
Bit [23:16] 2 I/O[ 7:0] 1 I/O[ 7:0]
st nd
Bit [15:8] 1 I/O[15:8] 2 I/O[15:8]
nd st
Bit [7:0] 1 I/O[ 7:0] 2 I/O[ 7:0]
nd st
B.
Half-word Access Register NFDATA Endian Little/Big Bit [31:24] Invalid value Bit [23:16] Invalid value Bit [15:8] 1 I/O[15:8]
st
Bit [7:0] 1 I/O[ 7:0]
st
2) 8-bit NAND Flash Memory Interface A. Word Access Register NFDATA NFDATA Endian Little Big Bit [31:24] 4 I/O[ 7:0] 1st I/O[ 7:0]
th
Bit [23:16] 3 I/O[ 7:0] 2nd I/O[ 7:0]
rd
Bit [15:8] 2 I/O[ 7:0] 3rd I/O[ 7:0]
nd
Bit [7:0] 1 I/O[ 7:0] 4th I/O[ 7:0]
st
B.
Half-word Access Register NFDATA NFDATA Endian Little Big Bit [31:24] Invalid value Invalid value Bit [23:16] Invalid value Invalid value Bit [15:8] 2 I/O[ 7:0] 1st I/O[ 7:0]
nd
Bit [7:0] 1 I/O[ 7:0] 2nd I/O[ 7:0]
st
C.
Byte Access Register NFDATA Endian Little/Big Bit [31:24] Invalid value Bit [23:16] Invalid value Bit [15:8] Invalid value Bit [7:0] 1 I/O[ 7:0]
st
STEPPINGSTONE (4K-Byte SRAM) The NAND Flash controller uses Steppingstone as the buffer on booting and also you can use this area for another purpose.
6-6
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
NAND FLASH CONTROLLER
ECC(Error Correction Code) NAND Flash controller has four ECC (Error Correction Code) modules. The two ECC modules (one for data[7:0] and the other for data[15:8]) can be used for (up to) 2048 bytes ECC Parity code generation, and the others(one for data[7:0] and the other for data[15:8]) can be used for (up to) 16 bytes ECC Parity code generation. 28bit ECC Parity Code = 22bit Line parity + 6bit Column Parity 14bit ECC Parity Code = 8bit Line parity + 6bit Column Parity
2048 BYTE ECC PARITY CODE ASSIGNMENT TABLE DATA7 MECCn_0 MECCn_1 MECCn_2 MECCn_3 P64 P1024 P4 P8192 DATA6 P64' P1024' P4' P8192' DATA5 P32 P512 P2 P4096 DATA4 P32' P512' P2' P4096' DATA3 P16 P256 P1 DATA2 P16' P256' P1' DATA1 P8 P128 P2048 DATA0 P8' P128' P2048' -
16 BYTE ECC PARITY CODE ASSIGNMENT TABLE DATA7 SECCn_0 SECCn_1 P16 P1 DATA6 P16' P1' DATA5 P8 P64 DATA4 P8' P64' DATA3 P4 P32 DATA2 P4' P32' DATA1 P2 DATA0 P2' -
6-7
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
NAND FLASH CONTROLLER
S3C2440X RISC MICROPROCESSOR
ECC MODULE FEATURES ECC generation is controlled by the ECC Lock (MainECCLock, SpareECCLock) bit of the Control register. ECC Register Configuration (Little / Big Endian) 1) 16-bit NAND Flash Memory Interface Register NFMECCD0 NFMECCD1
nd
Bit [31:24] 2 ECC for I/O[15:8] 4th ECC for I/O[15:8]
nd th
Bit [23:16] 2 ECC for I/O[7:0] 4 ECC for I/O[7:0]
st rd
Bit [15:8] 1 ECC for I/O[15:8] 3 ECC for I/O[15:8]
st rd
Bit [7:0] 1 ECC for I/O[7:0] 3 ECC for I/O[7:0]
Register NFSECCD
nd
Bit [31:24] 2 ECC for I/O[15:8]
nd
Bit [23:16] 2 ECC for I/O[7:0]
st
Bit [15:8] 1 ECC for I/O[15:8]
st
Bit [7:0] 1 ECC for I/O[7:0]
2) 8-bit NAND Flash Memory Interface Register NFMECCD0 NFMECCD1 Bit [31:24] nd th
Bit [23:16] 2 ECC for I/O[7:0] 4 ECC for I/O[7:0]
Bit [15:8] st rd
Bit [7:0] 1 ECC for I/O[7:0] 3 ECC for I/O[7:0]
Register NFSECCD
Bit [31:24] nd
Bit [23:16] 2 ECC for I/O[7:0]
Bit [15:8] st
Bit [7:0] 1 ECC for I/O[7:0]
ECC PROGRAMMING GUIDE 1) In software mode, ECC module generates ECC parity code for all read / write data. So you have to reset ECC value by writing the InitECC(NFCONT[4]) bit as `1' and have to clear theMainECCLock(NFCONT[5]) bit to `0'(Unlock) before read or write data. MainECCLock(NFCONT[5]) and SpareECCLock(NFCONT[6]) control whether ECC Parity code is generated or not. 2) Whenever data is read or written, the ECC module generates ECC parity code on register NFMECC0/1. 3) After you completely read or write one page (not include spare area data), Set the MainECCLock bit to `1'(Lock). ECC Parity code is locked and the value of the ECC status register will not be changed. 4) To generate spare area ECC parity code, Clear as `0'(Unlock) SpareECCLock(NFCONT[6]) bit. 5) Whenever data is read or written, the spare area ECC module generates ECC parity code on register NFSECC. 6) After you completely read or write spare area, Set the SpareECCLock bit to `1'(Lock). ECC Parity code is locked and the value of the ECC status register will not be changed. 7) From now, you can use these values to record to the spare area or check the bit error. (Note) NFSECCD is for ECC in the spare area (Usually, the user will write the ECC value of main data area to
6-8
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
NAND FLASH CONTROLLER
Spare area, which value will be the same as NFMECC0/1) and which is generated from the main data area.
NAND FLASH MEMORY MAPPING
0xFFFF_FFFF Not Used 0x6000_0000 SFR Area 0x4800_0000 0x4000_0FFF 0x4000_0000 BootSRAM (4KB) SDRAM 0x3800_0000 (BANK7, nGCS7) SDRAM (BANK6, nGCS6) SROM (BANK5, nGCS5) SROM (BANK4, nGCS4) SROM (BANK3, nGCS3) SROM 0x1000_0000 (BANK2, nGCS2) SROM 0x0800_0000 (BANK1, nGCS1) SROM (BANK0, nGCS0) OM[1:0] = 01, 10 Not Used SDRAM (BANK7, nGCS7) SDRAM (BANK6, nGCS6) SROM (BANK5, nGCS5) SROM (BANK4, nGCS4) SROM (BANK3, nGCS3) SROM (BANK2, nGCS2) SROM (BANK1, nGCS1) BootSRAM (4KB) OM[1:0] = 00 SFR Area Not Used
0x3000_0000
0x2800_0000
0x2000_0000
0x1800_0000
0x0000_0000
Figure 6-4. NAND Flash Memory Mapping Note: SROM means ROM or SRAM type memory
6-9
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
NAND FLASH CONTROLLER
S3C2440X RISC MICROPROCESSOR
NAND FLASH MEMORY CONFIGURATION
RnB nFRE nFCE CLE ALE nFWE R/ B RE CE CLE ALE WE I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0]
Figure 6-1 A 8-bit NAND Flash Memory Interface
Rn B nFRE nFCE CLE ALE nFWE
R/ B RE CE CLE ALE WE
I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0]
Rn B nFRE nFCE CLE ALE nFWE
R/ B RE CE CLE ALE WE
I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
DATA[15] DATA[14] DATA[13] DATA[12] DATA[11] DATA[10] DATA[9] DATA[8]
Figure 6-2 Two 8-bit NAND Flash Memory Interface
Rn B nFRE nFCE CLE ALE nFWE
R/ B RE CE CLE ALE WE
I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
DATA[15] DATA[14] DATA[13] DATA[12] DATA[11] DATA[10] DATA[9] DATA[8] DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0]
Figure 6-3 A 16-bit NAND Flash Memory Interface
6-10
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
NAND FLASH CONTROLLER
Nand Flash configuration Register
Register NFCONF Address 0x4E000000 R/W R/W Bit [15] [14:12] Reserved CLE & ALE duration setting value (0~7) Duration = HCLK x TACLS Reserved TWRPH0 [11] [10:8] Reserved TWRPH0 duration setting value (0~7) Duration = HCLK x ( TWRPH0 + 1 ) Reserved TWRPH1 [7] [6:4] Reserved TWRPH1 duration setting value (0~7) Duration = HCLK x ( TWRPH1 + 1 ) 0 000 0 000 Description NAND Flash Configuration register Description Reset Value 0x0000100X Initial State 001
NFCONF Reserved TACLS
6-11
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
NAND FLASH CONTROLLER
S3C2440X RISC MICROPROCESSOR
AdvFlash (Read only)
[3]
Advance NAND flash memory for auto-booting 0: Support 256 or 512 byte/page NAND flash memory 1: Support 1024 or 2048 byte/page NAND flash memory This bit is determined by NCON0 pin status during reset and wake-up from sleep mode.
H/W Set (NCON0)
PageSize (Read only)
[2]
NAND flash memory page size for auto-booting AdvFlash PageSize When AdvFlash is 0, 0: 256 Bytes/page, When AdvFlash is 1, 0: 1024 Bytes/page, 1: 2048 Bytes/page This bit is determined by GPG13 pin status during reset and wake-up from sleep mode. After reset, the GPG13 can be used as general I/O port or External interrupt. 1: 512 Bytes/page
H/W Set (GPG13)
AddrCycle (Read only)
[1]
NAND flash memory Address cycle for auto-booting AdvFlash AddrCycle When AdvFlash is 0, 0: 3 address cycle When AdvFlash is 1, 0: 4 address cycle 1: 5 address cycle This bit is determined by GPG14pin status during reset and wake-up from sleep mode. After reset, the GPG14can be used as general I/O port or External interrupt. 1: 4 address cycle
H/W Set (GPG14)
BusWidth (R/W)
[0]
NAND Flash Memory I/O bus width for auto-booting and general access. 0: 8-bit bus 1: 16-bit bus This bit is determined by GPG15 pin status during reset and wake-up from sleep mode. After reset, the GPG15 can be used as general I/O port or External interrupt. This bit can be changed by software.
H/W Set (GPG15)
6-12
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
NAND FLASH CONTROLLER
CONTROL REGISTER Register NFCONT Address 0x4E000004 R/W R/W Bit [14:15] [13] Reserved Lock-tight configuration 0: Disable lock-tight 1: Enable lock-tight, Once this bit is set to 1, you cannot clear. Only reset or wake up from sleep mode can make this bit disable(can not cleared by software). When it is set to 1, the area setting in NFSBLK(0x4E000038) to NFEBLK(0x4E00003C)-1 is unlocked, and except this area, write or erase command will be invalid and only read command is valid. When you try to write or erase locked area, the illegal access will be occur (NFSTAT[3] bit will be set). If the NFSBLK and NFEBLK are same, entire area will be locked. Soft Lock [12] Soft Lock configuration 0: Disable lock 1: Enable lock Soft lock area can be modified at any time by software. When it is set to 1, the area setting in NFSBLK(0x4E000038) to NFEBLK(0x4E00003C)-1 is unlocked, and except this area, write or erase command will be invalid and only read command is valid. When you try to write or erase locked area, the illegal access will be occur (NFSTAT[3] bit will be set). If the NFSBLK and NFEBLK are same, entire area will be locked. Reserved EnbIllegalAccINT [11] [10] Reserved Illegal access interrupt control 0: Disable interrupt 1: Enable interrupt Illegal access interrupt is occurs when CPU tries to program or erase locking area (the area setting in NFSBLK(0x4E000038) to NFEBLK(0x4E00003C)-1). EnbRnBINT RnB_TransMode [9] [8] RnB status input signal transition interrupt control 0: Disable RnB interrupt 0: Detect rising edge Reserved SpareECCLock [7] [6] Reserved Lock Spare area ECC generation. 1: Enable RnB interrupt 0 1: Detect falling edge 0 1 RnB transition detection configuration 0 0 0 1 Description NAND Flash control register Description Reset Value 0x0384 Initial State 0 0
NFCONT Reserved Lock-tight
6-13
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
NAND FLASH CONTROLLER
S3C2440X RISC MICROPROCESSOR
0: Unlock Spare ECC
1: Lock Spare ECC
Spare area ECC status register is NFSECC(0x4E000034), MainECCLock [5] Lock Main data area ECC generation 0: Unlock Main data area ECC generation 1: Lock Main data area ECC generation Main area ECC status register is NFMECC0/1(0x4E00002C/30), InitECC [4] Initialize ECC decoder/encoder(Write-only) 1: Initialize ECC decoder/encoder Reserved Reg_nCE [2:3] [1] Reserved NAND Flash Memory nFCE signal control 0: Force nFCE to low(Enable chip select) 1: Force nFCE to High(Disable chip select) Note: During boot time, it is controlled automatically. This value is only valid while MODE bit is 1 MODE [0] NAND Flash controller operating mode 0: NAND Flash Controller Disable (Don't work) 1: NAND Flash Controller Enable 0 00 1 0 1
6-14
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
NAND FLASH CONTROLLER
COMMAND REGISTER Register NFCMMD Address 0x4E000008 R/W R/W Bit [15:8] [7:0] Reserved NAND Flash memory command value Description NAND Flash command set register Description Reset Value 0x00 Initial State 0x00 0x00
NFCMMD Reserved NFCMMD ADDRESS REGISTER Register NFADDR Address 0x4E00000C
R/W R/W Bit [15:8] [7:0] Reserved
Description NAND Flash address set register Description NAND Flash memory address value
Reset Value 0x0000XX00 Initial State 0x00 0x00
REG_ADDR Reserved NFADDR DATA REGISTER Register NFDATA Address 0x4E000010
R/W R/W Bit [31:0]
Description NAND Flash data register Description NAND Flash read/program data value for I/O (Note) Refer to DATA REGISTER CONFIGURATION in p6-5.
Reset Value 0xXXXX Initial State 0xXXXX
NFDATA NFDATA
6-15
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
NAND FLASH CONTROLLER
S3C2440X RISC MICROPROCESSOR
MAIN DATA AREA REGISTER Register Address R/W R/W R/W
st
Description NAND Flash ECC 1 and 2 register for main data read (Note) Refer to ECC MODULE FEATURES in p6-8. NAND Flash ECC 3 4 register for main data read (Note) Refer to ECC MODULE FEATURES in p6-8.
rd th nd
Reset Value 0x00000000 0x00000000
NFMECCD0 0x4E000014 NFMECCD1 0x4E000018
NFMECCD0 ECCData1_1 ECCData1_0
Bit [31:24] [23:16] 2 ECC for I/O[15:8] 2 ECC for I/O[ 7:0]
nd nd
Description
Initial State 0x00 0x00
Note : In Software mode, Read this register when you nd need to read 2 ECC value from NAND flash memory ECCData0_1 ECCData0_0 [15:8] [7:0] 1 ECC for I/O[15:8] 1 ECC for I/O[ 7:0] Note : In Software mode, Read this register when you need to read 1st ECC value from NAND flash memory. This register has same read function of NFDATA. (Note) Only word access is valid. NFMECCD1 ECCData3_1 ECCData3_0 Bit [31:24] [23:16] 4th ECC for I/O[15:8] 4 ECC for I/O[ 7:0] Note : In Software mode, Read this register when you need to read 4th ECC value from NAND flash memory ECCData2_1 ECCData2_0 [15:8] [7:0] 3 ECC for I/O[15:8] 3 ECC for I/O[ 7:0] Note: In Software mode, Read this register when you need rd to read 3 ECC value from NAND flash memory. This register has same read function of NFDATA. (Note) Only word access is valid. Important Note MAIN DATA AREA REGISTER (NFMECCD0/1) does not meet the specification. Next revision chip will meet the specification. Workaround: ECC detection by software
rd rd th st st
0x00 0x00
Description
Initial State 0x00 0x00
0x00 0x00
6-16
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
NAND FLASH CONTROLLER
SPARE AREA ECC REGISTER Register NFSECCD Address 0x4E00001C R/W Description Reset Value R/W NAND Flash ECC(Error Correction Code) register for spare 0x00000000 area data read
NFSECCD ECCData1_1 ECCData1_0
Bit [31:24] [23:16] 2 ECC for I/O[15:8] 2 ECC for I/O[ 7:0]
nd nd
Description
Initial State 0x00 0x00
Note: In Software mode, Read this register when you need to read 2nd ECC value from NAND flash memory ECCData0_1 ECCData0_0 [15:8] [7:0] 1 ECC for I/O[15:8] 1 ECC for I/O[ 7:0] Note: In Software mode, Read this register when you need to st read 1 ECC value from NAND flash memory. This register has same read function of NFDATA. (Note) Only word access is valid.
st st
0x00 0x00
6-17
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
NAND FLASH CONTROLLER
S3C2440X RISC MICROPROCESSOR
NFCON STATUS REGISTER Register NFSTAT NFSTAT Reserved Reserved IllegalAccess Address R/W Description Reset Value 0xXX00 Initial State X 0 0 0x4E000020 R/W NAND Flash operation status register Bit [7] [4:6] [3] Reserved Reserved Once Soft Lock or Lock-tight is enabled, The illegal access (program, erase) to the memory makes this bit set. 0: illegal access is not detected 1: illegal access is detected RnB_TransDetect [2] When RnB low to high transition is occurred, this value set and issue interrupt if enabled. To clear this value write `1'. 0: RnB transition is not detected 1: RnB transition is detected Transition configuration is set in RnB_TransMode(NFCONT[8]). nCE (Read-only) RnB (Read-only) [0] The status of RnB input pin. 0: NAND Flash memory busy 1: NAND Flash memory ready to operate 1 [1] The status of nCE output pin 1 0 Description
6-18
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
NAND FLASH CONTROLLER
ECC0/1 STATUS REGISTER Register NFESTAT0 NFESTAT1 NFESTAT0 SErrorDataNo SErrorBitNo MErrorDataNo MErrorBitNo SpareError Address 0x4E000024 0x4E000028 Bit [24:21] [20:18] [17:7] [6:4] [3:2] R/W Description Reset Value 0x00000000 0x00000000 Initial State 00 000 0x00 000 00 R/W NAND Flash ECC Status register for I/O [7:0] R/W NAND Flash ECC Status register for I/O [15:8] Description In spare area, Indicates which number data is error In spare area, Indicates which bit is error In main data area, Indicates which number data is error In main data area, Indicates which bit is error Indicates whether spare area bit fail error occurred 00: No Error 10: Multiple error MainError [1:0] 00: No Error 10: Multiple error 01: 1-bit error(correctable) 11: ECC area error 00 01: 1-bit error(correctable) 11: ECC area error
Indicates whether main data area bit fail error occurred
Note : The above values are only valid when both ECC register and ECC status register have valid value.
NFESTAT1 SErrorDataNo SErrorBitNo MErrorDataNo MErrorBitNo SpareError
Bit [24:21] [20:18] [17:7] [6:4] [3:2]
Description In spare area, Indicates which number data is error In spare area, Indicates which bit is error In main data area, Indicates which number data is error In main data area, Indicates which bit is error Indicates whether spare area bit fail error occurred 00: No Error 10: Multiple error 01: 1-bit error(correctable) 11: ECC area error
Initial State 00 000 0x00 000 00
MainError
[1:0]
Indicates whether main data area bit fail error occurred 00: No Error 10: Multiple error 01: 1-bit error(correctable) 11: ECC area error
00
Note : The above values are only valid when both ECC register and ECC status register have valid value.
6-19
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
NAND FLASH CONTROLLER
S3C2440X RISC MICROPROCESSOR
MAIN DATA AREA ECC0 STATUS REGISTER Register Address R/W R R Description NAND Flash ECC register for data[7:0] NAND Flash ECC register for data[15:8] Reset Value 0xXXXXXX 0xXXXXXX NFMECC0 0x4E00002C NFMECC1 0x4E000030
NFMECC0 MECC0_3 MECC0_2 MECC0_1 MECC0_0
Bit [31:24] [23:16] [15:8] [7:0] ECC3 for data[7:0] ECC2 for data[7:0] ECC1 for data[7:0] ECC0 for data[7:0]
Description
Initial State 0xXX 0xXX 0xXX 0xXX
NFMECC1 MECC1_3 MECC1_2 MECC1_1 MECC1_0
Bit [31:24] [23:16] [15:8] [7:0] ECC3 data[15:8] ECC2 data[15:8] ECC1 data[15:8] ECC0 data[15:8]
Description
Initial State 0xXX 0xXX 0xXX 0xXX
(Note) The NAND flash controller generate NFMECC0/1 when read or write main area data while the MainECCLock(NFCONT[5]) bit is `0'(Unlock). SPARE AREA ECC STATUS REGISTER Register NFSECC Address 0x4E000034 R/W R Bit [31:24] [23:16] [15:8] [7:0] Description NAND Flash ECC register for I/O [15:0] Description Spare area ECC1 Status for I/O[15:8] Spare area ECC0 Status for I/O[15:8] Spare area ECC1 Status for I/O[7:0] Spare area ECC0 Status for I/O[7:0] Reset Value 0xXXXXXX Initial State 0xXX 0xXX 0xXX 0xXX
NFSECC SECC1_1 SECC1_0 SECC0_1 SECC0_0
(Note) The NAND flash controller generate NFSECC when read or write spare area data while the SpareECCLock(NFCONT[6]) bit is `0'(Unlock).
6-20
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
NAND FLASH CONTROLLER
BLOCK ADDRESS REGISTER Register NFSBLK NFEBLK Address 0x4E000038 0x4E00003C R/W R/W R/W Description NAND Flash programmable start block address NAND Flash programmable end block address Nand Flash can be programmed between start and end address. When the Soft lock or Lock-tight is enabled and the Start and End address has same value, Entire area of NAND flash will be locked. NFSBLK SBLK_ADDR2 SBLK_ADDR1 SBLK_ADDR0 Bit [23:16] [15:8] [7:0]
rd nd st
Reset Value 0x000000 0x000000
Description The 3 block address of the block erase operation The 2 block address of the block erase operation The 1 block address of the block erase operation (Only bit [7:5] are valid)
Initial State 0x00 0x00 0x00
.
Note : Advance Flash's block Address start from 3-address cycle. So block address register only needs 3-bytes
NFEBLK EBLK_ADDR2 EBLK_ADDR1 EBLK_ADDR0
Bit [23:16] [15:8] [7:0]
rd nd st
Description The 3 block address of the block erase operation The 2 block address of the block erase operation The 1 block address of the block erase operation (Only bit [7:5] are valid)
Initial State 0x00 0x00 0x00
Note : Advance Flash's block Address start from 3-address cycle. So block address register only needs 3-bytes.
The NFSLK and NFEBLK can be changed while Soft lock bit(NFCONT[12]) is enabled. But cannot be changed when Lock-tight bit(NFCONT[13]) is set. NAND flash memory Address Locked area (Read only) NFEBLK NFEBLK-1 Prorammable/ Readable Area NFSBLK Locked area (Read only) Low when Lock-tight =1 or SoftLock=1 NFSBLK NFEBLK Locked Area (Read only) High When NFSBLK=NFEBLK
6-21
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
CLOCK & POWER MANAGEMENT
CLOCK & POWER MANAGEMENT
OVERVIEW
The clock & power management block consists of three parts: Clock control, USB control, and Power control. The Clock control logic in S3C2440X can generate the required clock signals including FCLK for CPU, HCLK for the AHB bus peripherals, and PCLK for the APB bus peripherals. The S3C2440X has two Phase Locked Loops (PLLs): one for FCLK, HCLK, and PCLK, and the other dedicated for USB block (48Mhz). The clock control logic can make slow clocks without PLL and connect/disconnect the clock to each peripheral block by software, which will reduce the power consumption. For the power control logic, the S3C2440X has various power management schemes to keep optimal power consumption for a given task. The power management block in the S3C2440X can activate four modes: NORMAL mode, SLOW mode, IDLE mode, and SLEEP mode. NORMAL mode: The block supplies clocks to CPU as well as all peripherals in the S3C2440X. In this mode, the power consumption will be maximized when all peripherals are turned on. It allows the user to control the operation of peripherals by software. For example, if a timer is not needed, the user can disconnect the clock to the timer to reduce power consumption. SLOW mode: Non-PLL mode. Unlike the Normal mode, the Slow mode uses an external clock (XTIpll or EXTCLK) directly as FCLK in the S3C2440X without PLL. In this mode, the power consumption depends on the frequency of the external clock only. The power consumption due to PLL is excluded. IDLE mode: The block disconnects clocks (FCLK) only to the CPU core while it supplies clocks to all other peripherals. The IDLE mode results in reduced power consumption due to CPU core. Any interrupt request to CPU can be woken up from the Idle mode. SLEEP mode: The block disconnects the internal power. So, there occurs no power consumption due to CPU and the internal logic except the wake-up logic in this mode. Activating the SLEEP mode requires two independent power sources. One of the two power sources supplies the power for the wake-up logic. The other one supplies other internal logics including CPU, and should be controlled for power on/off. In the SLEEP mode, the second power supply source for the CPU and internal logics will be turned off. The wakeup from SLEEP mode can be issued by the EINT[15:0] or by RTC alarm interrupt.
7-1
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
CLOCK & POWER MANAGEMENT
S3C2440X
FUNCTIONAL DESCRIPTION
CLOCK ARCHITECTURE Figure 7-1 shows a block diagram of the clock architecture. The main clock source comes from an external crystal (XTIpll) or an external clock (EXTCLK). The clock generator includes an oscillator (Oscillation Amplifier), which is connected to an external crystal, and also has two PLLs (Phase-Locked-Loop), which generate the high frequency clock required in the S3C2440X. CLOCK SOURCE SELECTION Table 7-1 shows the relationship between the combination of mode control pins (OM3 and OM2) and the selection of source clock for the S3C2440X. The OM[3:2] status is latched internally by referring the OM3 and OM2 pins at the rising edge of nRESET. Table 7-1. Clock Source Selection at Boot-Up Mode OM[3:2] 00 01 10 11 MPLL State On On On On UPLL State On On On On Main Clock source Crystal Crystal EXTCLK EXTCLK USB Clock Source Crystal EXTCLK Crystal EXTCLK
NOTE: 1. Although the MPLL starts just after a reset, the MPLL output (Mpll) is not used as the system clock until the software writes valid settings to the MPLLCON register. Before this valid setting, the clock from external crystal or EXTCLK source will be used as the system clock directly. Even if the user does not want to change the default value of MPLLCON register, the user should write the same value into MPLLCON register. 2. OM[3:2] is used to determine a test mode when OM[1:0] is 11.
7-2
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X
CLOCK & POWER MANAGEMENT
OM[3:2] XTIpll XTOpll EXTCLK OSC
P[5:0] M[7:0] S[1:0] MPLL Mpll CLKCNTL FCLK Control Signal USBCNTL
HDIVN PDIVN
MPLL CLK UPLL CLK HCLK PCLK FCLK
CLKOUT
F
H P POWCNTL
DIVN_UPLL 1/1 or 1/2
Upll UPLL
P[5:0] M[7:0] S[1:0]
Power Management Block
Test mode OM[1:0]
UCLK
HCLK PCLK Nand Flash Controller H_USB H_Nand H_CAM
FCLK Memory Controller
ARM920T Interrupt Controller H_LCD LCD Controller
USB Host I/F
CAMDIVN
CAM
TIC
ExtMater
Bus Controller Arbitration DMA 4ch
WDT P_PWM PWM USB Device
I2S P_I2S P_I2C I 2C
SDI P_SDI P_GPIO GPIO
ADC P_ADC P_RTC RTC
UART(0,1,2) P_UART P_SPI SPI(0,1)
P_USB
Figure 7-1. Clock Generator Block Diagram
7-3
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
CLOCK & POWER MANAGEMENT
S3C2440X
PHASE LOCKED LOOP (PLL) The MPLL within the clock generator, as a circuit, synchronizes an output signal with a reference input signal in frequency and phase. In this application, it includes the following basic blocks as shown in Figure 7-2: the Voltage Controlled Oscillator (VCO) to generate the output frequency proportional to input DC voltage, the divider P to divide the input frequency (Fin) by p, the divider M to divide the VCO output frequency by m which is input to Phase Frequency Detector (PFD), the divider S to divide the VCO output frequency by s which is Mpll (the output frequency from MPLL block), the phase difference detector, the charge pump, and the loop filter. The output clock frequency Mpll is related to the reference input clock frequency Fin by the following equation: Mpll = (m * Fin) / (p * 2s) m = M (the value for divider M)+ 8, p = P (the value for divider P) + 2 The UPLL within the clock generator is the same as the MPLL in every aspect. The following sections describes the operation of the PLL, including the phase difference detector, the charge pump, the Voltage controlled oscillator (VCO), and the loop filter. Phase Difference Detector (PFD) The PFD monitors the phase difference between Fref and Fvco, and generates a control signal (tracking signal) when the difference is detected. The Fref means the reference frequency as shown in the Figure 7-2. Charge Pump (PUMP) The charge pump converts PFD control signals into a proportional charge in voltage across the external filter that drives the VCO. Loop Filter The control signal, which the PFD generates for the charge pump, may generate large excursions (ripples) each time the Fvco is compared to the Fref. To avoid overloading the VCO, a low pass filter samples and filters the high-frequency components out of the control signal. The filter is typically a single-pole RC filter with a resistor and a capacitor. Voltage Controlled Oscillator (VCO) The output voltage from the loop filter drives the VCO, causing its oscillation frequency to increase or decrease linearly as a function of variations in average voltage. When the Fvco matches Fref in terms of frequency as well as phase, the PFD stops sending control signals to the charge pump, which in turn stabilizes the input voltage to the loop filter. The VCO frequency then remains constant, and the PLL remains fixed onto the system clock. Usual Conditions for PLL & Clock Generator PLL & Clock Generator generally uses the following conditions. Loop filter capacitance External X-tal frequency External capacitance used for X-tal CLF CEXT MPLLCAP: 2.8 nF UPLLCAP: 700 pF 10 - 20 MHz (note) 15 - 22 pF
NOTES: 1. The value could be changed. 2. FCLK must be more than three times X-tal or EXTCLK (FCLK 3X-tal or 3EXTCLK)
7-4
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X
CLOCK & POWER MANAGEMENT
Fin
Divider P
Fref PFD PUMP
Loop Filter
P[5:0] Fvco M[7:0] Divider M VCO
R C
MPLLCAP, UPLLCAP CLF
Internal External
S[1:0]
Divider S
MPLL,UPLL
Figure 7-2. PLL (Phase-Locked Loop) Block Diagram
VDD EXTCLK External OSC VDD XTIpll XTIpll EXTCLK
CEXT
CEXT XTOpll XTOpll
a) X-TAL Oscillation (OM[3:2]=00)
b) External Clock Source (OM[3:2]=11)
Figure 7-3. Main Oscillator Circuit Examples
7-5
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
CLOCK & POWER MANAGEMENT
S3C2440X
CLOCK CONTROL LOGIC The clock control logic determines the clock source to be used, i.e., the PLL clock (Mpll) or the direct external clock (XTIpll or EXTCLK). When PLL is configured to a new frequency value, the clock control logic disables the FCLK until the PLL output is stabilized using the PLL locking time. The clock control logic is also activated at power-on reset and wakeup from power-down mode. Power-On Reset (XTIpll) Figure 7-4 shows the clock behavior during the power-on reset sequence. The crystal oscillator begins oscillation within several milliseconds. When nRESET is released after the stabilization of OSC (XTIpll) clock, the PLL starts to operate according to the default PLL configuration. However, PLL is commonly known to be unstable after power-on reset, so Fin is fed directly to FCLK instead of the Mpll (PLL output) before the software newly configures the PLLCON. Even if the user does not want to change the default value of PLLCON register after reset, the user should write the same value into PLLCON register by software. The PLL restarts the lockup sequence toward the new frequency only after the software configures the PLL with a new frequency. FCLK can be configured as PLL output (Mpll) immediately after lock time.
Power PLL can operate after OM[3:2] is latched. nRESET
OSC (XTIpll) PLL is configured by S/W first time. Clock Disable Lock Time VCO is adapted to new clock frequency. VCO output
FCLK The logic operates by XTIpll FCLK is new frequency
Figure 7-4. Power-On Reset Sequence (when the external clock source is a crystal oscillator)
7-6
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X
CLOCK & POWER MANAGEMENT
Change PLL Settings In Normal Operation Mode During the operation of the S3C2440X in NORMAL mode, the user can change the frequency by writing the PMS value and the PLL lock time will be automatically inserted. During the lock time, the clock is not supplied to the internal blocks in the S3C2440X. Figure 7-5 shows the timing diagram.
Mpll PMS setting PLL Lock-time FCLK It changes to new PLL clock after automatic lock time.
Figure 7-5. Changing Slow Clock by Setting PMS Value
USB Clock Control USB host interface and USB device interface needs 48Mhz clock. In the S3C2440X, the USB dedicated PLL (UPLL) generates 48Mhz for USB. UCLK does not fed until the PLL (UPLL) is configured. Condition After reset After configuring UPLL UPLL is turned off by CLKSLOW register UPLL is turned on by CLKSLOW register L UCLK State XTlpll or EXTCLK : during PLL lock time 48MHz: after PLL lock time XTlpll or EXTCLK 48MHz Off On UPLL State On On
7-7
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
CLOCK & POWER MANAGEMENT
S3C2440X
FCLK, HCLK, and PCLK FCLK is used by ARM920T. HCLK is used for AHB bus, which is used by the ARM920T, the memory controller, the interrupt controller, the LCD controller, the DMA and USB host block. PCLK is used for APB bus, which is used by the peripherals such as WDT, IIS, I2C, PWM timer, MMC interface, ADC, UART, GPIO, RTC and SPI. The S3C2440X supports selection of Dividing Ratio between FCLK, HLCK and PCLK. This ratio is determined by HDIVN and PDIVN of CLKDIVN control register. HDIVN 0 0 1 1 3 3 2 2 PDIVN 0 1 0 1 0 1 0 1 FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK HCLK FCLK FCLK FCLK / 2 FCLK / 2 FCLK / 3 FCLK / 3 FCLK / 4 FCLK / 4 PCLK FCLK FCLK / 2 FCLK / 2 FCLK / 4 FCLK / 3 FCLK / 6 FCLK / 4 FCLK / 8 Divide Ratio 1:1:1 (Default) 1:1:2 1:2:2 1:2:4 1:3:3 1:3:6 1:4:4 1:4:8
After setting PMS value, it is required to set CLKDIVN register. The value set for CLKDIVN will be valid after PLL lock time. The value is also available for reset and changing Power Management Mode. The setting value can also be valid after 1.5 HCLK. Only, 1HCLK can validate the value of CLKDIVN register changed from Default (1:1:1) to other Divide Ratio (1:1:2, 1:2:2 and 1:2:4)
FCLK CLKDIVN HCLK PCLK 1 HCLK 1.5 HCLK 1.5 HCLK 0x00000000 0x00000001(1:1:2) 0x00000003 (1:2:4) 0x00000000 (1:1:1)
Figure 7-6. Changing CLKDIVN Register Value
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X
CLOCK & POWER MANAGEMENT
NOTE 1. CLKDIVN should be set carefully not to exceed the limit of HCLK and PCLK. 2. If HDIVN is not 0, the CPU bus mode has to be changed from the fast bus mode to the asynchronous bus mode using following instructions. MMU_SetAsyncBusMode mrc p15,0,r0,c1,c0,0 orr r0,r0,#R1_nF:OR:R1_iA mcr p15,0,r0,c1,c0,0 If HDIVN is not 0 and the CPU bus mode is the fast bus mode, the CPU will operate by the HCLK. This feature can be used to change the CPU frequency as a half or more without affecting the HCLK and PCLK.
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
CLOCK & POWER MANAGEMENT
S3C2440X
POWER MANAGEMENT The Power Management block controls the system clocks by software for the reduction of power consumption in the S3C2440X. These schemes are related to PLL, clock control logics (FCLK, HCLK, and PCLK) and wakeup signals. Figure 7-7 shows the clock distribution of the S3C2440X. The S3C2440X has four power modes. The following section describes each power management mode. The transition between the modes is not allowed freely. Please see Figure 7-8 for available transitions among the modes.
Clock Control Register
ARM920T
WDT MEMCNTL SPI INTCNTL PWM BUSCNTL I2C ARB/DMA SDI ExtMaster ADC LCDCNTL UART Nand Flash Controller I2S Camera USB Host I/F GPIO RTC USB Device
FCLK HCLK Input Clock
Power Management
PCLK UPLL(96/48 MHz)
FCLK defination If SLOW mode FCLK = input clock/divider ratio If Normal mode (P, M & S value) FCLK = MPLL clock (Mpll) 1/d 1/2 1/1
Figure 7-7. The Clock Distribution Block Diagram
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X
CLOCK & POWER MANAGEMENT
IDLE_BIT=1 IDLE Interrupts, EINT[0:23], RTC alarm
RESET
NORMAL (SLOW_BIT=0) EINT[15:0], RTC alarm SLOW (SLOW_BIT=1)
SLEEP BIT=1
SLEEP
Figure 7-8. Power Management State Diagram
Table 7-2. Clock and Power State in Each Power Mode Mode NORMAL IDLE SLOW SLEEP ARM920T O X O OFF Power AHB Modules (1) Management /WDT O O O OFF O O O GPIO SEL SEL SEL 32.768kHz RTC clock O O O O APB Modules (2) & USBH/LCD/NAND SEL SEL SEL OFF
Wait for wake- Previous up event state
NOTES: 1. USB host,LCD, and NAND are excluded. 2. WDT is excluded. RTC interface for CPU access is included. 3. SEL : selectable(O,X), O : enable , X : disable OFF: power is turned off
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
CLOCK & POWER MANAGEMENT
S3C2440X
NORMAL Mode In Normal mode, all peripherals and the basic blocks including power management block, the CPU core, the bus controller, the memory controller, the interrupt controller, DMA, and the external master may operate fully. But, the clock to each peripheral, except the basic blocks, can be stopped selectively by software to reduce the power consumption.
IDLE Mode In IDLE mode, the clock to the CPU core is stopped except the bus controller, the memory controller, the interrupt controller, and the power management block. To exit the IDLE mode, EINT[23:0], or RTC alarm interrupt, or the other interrupts should be activated. (EINT is not available until GPIO block is turned on).
SLOW Mode (Non-PLL Mode) Power consumption can be reduced in the SLOW mode by applying a slow clock and excluding the power consumption from the PLL. The FCLK is the frequency of divide_by_n of the input clock (XTIpll or EXTCLK) without PLL. The divider ratio is determined by SLOW_VAL in the CLKSLOW control register and CLKDIVN control register. Table 7-3. CLKSLOW and CLKDIVN Register Settings for SLOW Clock example SLOW_VAL FCLK HCLK 1/1 Option (HDIVN=0) 000 001 010 011 100 101 110 111 EXTCLK or XTIpll / 1 EXTCLK or XTIpll / 2 EXTCLK or XTIpll / 4 EXTCLK or XTIpll / 6 EXTCLK or XTIpll / 8 EXTCLK or XTIpll / 10 EXTCLK or XTIpll / 12 EXTCLK or XTIpll / 14 EXTCLK or XTIpll / 1 EXTCLK or XTIpll / 2 EXTCLK or XTIpll / 4 EXTCLK or XTIpll / 6 EXTCLK or XTIpll / 8 EXTCLK or XTIpll / 10 EXTCLK or XTIpll / 12 EXTCLK or XTIpll / 14 1/2 Option (HDIVN=1) EXTCLK or XTIpll / 2 EXTCLK or XTIpll / 4 EXTCLK or XTIpll / 8 EXTCLK or XTIpll / 12 EXTCLK or XTIpll / 16 EXTCLK or XTIpll / 20 EXTCLK or XTIpll / 24 EXTCLK or XTIpll / 28 PCLK 1/1 Option (PDIVN=0) HCLK HCLK HCLK HCLK HCLK HCLK HCLK HCLK 1/2 Option (PDIVN=1) HCLK / 2 HCLK / 2 HCLK / 2 HCLK / 2 HCLK / 2 HCLK / 2 HCLK / 2 HCLK / 2 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz UCLK
In SLOW mode, PLL will be turned off to reduce the PLL power consumption. When the PLL is turned off in the SLOW mode and the user changes power mode from SLOW mode to NORMAL mode, the PLL needs clock stabilization time (PLL lock time). This PLL stabilization time is automatically inserted by the internal logic with lock time count register. The PLL stability time will take 300us after the PLL is turned on. During PLL lock time, the FCLK becomes SLOW clock.
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X
CLOCK & POWER MANAGEMENT
Users can change the frequency by enabling SLOW mode bit in CLKSLOW register in PLL on state. The SLOW clock is generated during the SLOW mode. Figure 7-11 shows the timing diagram.
Mpll SLOW_BIT MPLL_OFF FCLK Divided external clock It changes to PLL clock after slow mode off Slow mode enable Slow mode disable
Figure 7-9. Issuing Exit_from_Slow_mode Command in PLL on State
If the user switches from SLOW mode to Normal mode by disabling the SLOW_BIT in the CLKSLOW register after PLL lock time, the frequency is changed just after SLOW mode is disabled. Figure 7-12 shows the timing diagram.
Software lock time Mpll SLOW_BIT MPLL_OFF FCLK Divided OSC clock It changes to PLL clock after slow mode off Slow mode enable PLL off Slow mode disable PLL on
Figure 7-10. Issuing Exit_from_Slow_mode Command After Lock Time
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
CLOCK & POWER MANAGEMENT
S3C2440X
If the user switches from SLOW mode to Normal mode by disabling SLOW_BIT and MPLL_OFF bit simultaneously in the CLKSLOW register, the frequency is changed just after the PLL lock time. Figure 7-13 shows the timing diagram.
Hardware lock time Mpll SLOW_BIT MPLL_OFF FCLK Divided OSC clock It changes to PLL clock after lock time automatically Slow mode enable PLL off Slow mode disable PLL on
Figure 7-11. Issuing Exit_from_Slow_mode Command and the Instant PLL_on Command Simultaneously
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X
CLOCK & POWER MANAGEMENT
SLEEP Mode The block disconnects the internal power. So, there occurs no power consumption due to CPU and the internal logic except the wake-up logic in this mode. Activating the SLEEP mode requires two independent power sources. One of the two power sources supplies the power for the wake-up logic. The other one supplies other internal logics including CPU, and should be controlled for power on/off. In the SLEEP mode, the second power supply source for the CPU and internal logics will be turned off. The wakeup from SLEEP mode can be issued by the EINT[15:0] or by RTC alarm interrupt.
Follow the Procedure to Enter SLEEP mode 1. Set the GPIO configuration adequate for SLEEP mode. 2. Mask all interrupts in the INTMSK register. 3. Configure the wake-up sources properly including RTC alarm. (The bit of EINTMASK corresponding to the wake-up source has not to be masked in order to let the corresponding bit of SRCPND or EINTPEND set. Although a wake-up source is issued and the corresponding bit of EINTMASK is masked, the wake-up will occur and the corresponding bit of SRCPND or EINTPEND will not be set.) 4. Set USB pads as suspend mode. (MISCCR[13:12]=11b) 5. Save some meaning values into GSTATUS[4:3] register. These register are preserved during SLEEP mode. 6. Configure MISCCR[1:0] for the pull-up resisters on the data bus,D[31:0]. If there is an external BUS holder, such as 74LVCH162245, turn off the pull-up resistors. If not, turn on the pull-up resistors. Additionally, The Memory concerning pins are set to two type, one is Hi-z, and the other is Inactive state. 7. Stop LCD by clearing LCDCON1.ENVID bit. 8. Read rREFRESH and rCLKCON registers in order to fill the TLB. 9. Let SDRAM enter the self-refresh mode by setting the REFRESH[22]=1b. 10. Wait until SDRAM self-refresh is effective. 11. Set MISCCR[19:17]=111b to make SDRAM signals(SCLK0,SCLK1 and SCKE) protected during SLEEP mode 12. Set the SLEEP mode bit in the CLKCON register.
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
CLOCK & POWER MANAGEMENT
S3C2440X
Follow the Procedure to Wake-up from SLEEP mode 1. The internal reset signal will be asserted if one of the wake-up sources is issued. It's exactly same with the case of the assertion of the external nRESET pin. This reset duration is determined by the internal 16-bit counter logic and the reset assertion time is calculated as tRST = (65535 / XTAL_frequency). 2. Check GSTATUS2[2] in order to know whether or not the power-up is caused by the wake-up from SLEEP mode. 3. Release the SDRAM signal protection by setting MISCCR[19:17]=000b. 4. Configure the SDRAM memory controller. 5. Wait until the SDRAM self-refresh is released. Mostly SDRAM needs the refresh cycle of all SDRAM row. 6. The information in GSTATUS[3:4] can be used for user's own purpose because the value in GSTATUS[3:4] has been preserved during SLEEP mode. 7. - For EINT[3:0], check the SRCPND register. - For EINT[15:4], check the EINTPEND instead of SRCPND (SRCPND will not be set although some bits of EINTPEND are set.). - For alarm wake-up, check the RTC time because the RTC bit of SRCPND isn't set at the alarm wake-up. - If there was the nBATT_FLT assertion during SLEEP mode, the corresponding bit of SRCPND has been set. Pin States in SLEEP Mode The pin state of the SLEEP mode is as follows; Pin Type GPIO output pin GPIO input pin GPIO bi-directional pin Function output pin Function input pin Pin Example GPB0:input GPB0:output GPG6:SPIMOSI nGCS0 nWAIT Input Input Output (the last output level is held.) Input Pin States in SLEEP Mode Output ( GPIO data register value is used.)
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2003.09.25
S3C2440X
CLOCK & POWER MANAGEMENT
Power Control of VDDi and VDDiarm In SLEEP mode, only VDDi and VDDiarm will be turned off, which is controlled by PWREN pin. If PWREN signal is active(H), VDDi and VDDiarm are supplied by an external voltage regulator. If PWREN pin is inactive (L), the VDDi and VDDiarm are turned off. NOTE Although VDDi and VDDiarm may be turned off, the other power pins have to be supplied.
1.2V Regulator 1.2V EN PWREN
1.2V Power
VDDalive
S3C2440X
RTC Alarm VDDi VDDiarm VDDMPLL VDDUPLL Power CTRL (Alive Block) EINT
RTC
External Interrupt Core & Peripherals I/O 3.3V Power
Figure 7-12. SLEEP Mode
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2003.09.25
CLOCK & POWER MANAGEMENT
S3C2440X
Signaling EINT[15:0] for Wakeup The S3C2440X can be woken up from SLEEP mode only if the following conditions are met. a) Level signals (H or L) or edge signals (rising or falling or both) are asserted on EINTn input pin. b) The EINTn pin has to be configured as EINT in the GPIO control register. c) nBATT_FLT pin has to be H level. It is important to configure the EINTn in the GPIO control register as an external interrupt pins, considering the condition a) above. Just after the wake-up, the corresponding EINTn pin will not be used for wakeup. This means that the pin can be used as an external interrupt request pin again. Entering IDLE Mode If CLKCON[2] is set to 1 to enter the IDLE mode, the S3C2440X will enter IDLE mode after some delay (until the power control logic receives ACK signal from the CPU wrapper). PLL On/Off The PLL can only be turned off for low power consumption in slow mode. If the PLL is turned off in any other mode, MCU operation is not guaranteed. When the processor is in SLOW mode and tries to change its state into other state with the PLL turned on, then SLOW_BIT should be clear to move to another state after PLL stabilization Pull-up Resistors on the Data Bus and SLEEP Mode In SLEEP mode, the data bus (D[31:0] or D[15:0] ) is in Hi-z state. But, because of the characteristics of I/O pad, the data bus pull-up resistors have to be turned on for low power consumption in SLEEP mode. D[31:0] pin pull-up resistors can be controlled by the GPIO control register (MISCCR). However, if there is an external bus holder, such as 74LVCH162245, on the data bus, turning off the data bus pull-up resistors will be reduce power consumption.
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2003.09.25
S3C2440X
CLOCK & POWER MANAGEMENT
Output Port State and SLEEP Mode If output is L, the current will be consumed through the internal parasitic resistance; if the output is H, the current will not be consumed. For an output port, the current consumption can be reduced if the output state is H. It is recommended that the output ports be in H state to reduce current consumption in SLEEP mode. Battery Fault Signal(nBATT_FLT) There are two functions in nBATT_FLT pin as follows; -- When CPU is not in SLEEP mode, nBATT_FLT pin will cause the interrupt request. The interrupt attribute of the nBATT_FLT is L-level triggered. -- While CPU is in SLEEP mode, assertion of the nBATT_FLT will prohibit the wake up from the power-down mode. So, Any wake-up source will be masked if nBATT_FLT is asserted, which is protecting the system malfunction of the low battery capacity
ADC Power Down The ADC has an additional power-down bit in ADCCON. If the S3C2440X enters the SLEEP mode, the ADC should enter its own power-down mode.
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
CLOCK & POWER MANAGEMENT
S3C2440X
CLOCK GENERATOR & POWER MANAGEMENT SPECIAL REGISTER
LOCK TIME COUNT REGISTER (LOCKTIME) Register LOCKTIME Address 0x4C000000 R/W R/W Description PLL lock time count register Reset Value 0xFFFFFFFF
LOCKTIME U_LTIME M_LTIME
Bit [31:16] [15:0]
Description UPLL lock time count value for UCLK. (U_LTIME 300uS) MPLL lock time count value for FCLK, HCLK, and PCLK (M_LTIME 300uS)
Initial State 0xFFFF 0xFFFF
PLL Control Register (MPLLCON and UPLLCON) Mpll = (m * Fin) / (p * 2s) m = (MDIV + 8), p = (PDIV + 2), s = SDIV PLL Value Selection Guide (MPLLCON) 1. Fout = m * Fin / (p*2s), Fvco = m * Fin / p where : m=MDIV+8, p=PDIV+2, s=SDIV 2. 200MHz Fvco 500MHz 3. 100MHz Fout 500MHz (The max. Fout of the PLL itself is 500MHz) 4. FCLK 3X-tal or 3EXTCLK
NOTE: Although there is the rule for choosing PLL value, we recommend only the values in the PLL value recommendation table. If you have to use another value, please contact us.
Register MPLLCON UPLLCON PLLCON MDIV PDIV SDIV
Address 0x4C000004 0x4C000008 Bit [19:12] [9:4] [1:0]
R/W R/W R/W
Description MPLL configuration register UPLL configuration register Description Main divider control Pre-divider control Post divider control
Reset Value 0x00096030 0x0004d030 Initial State 0x96 / 0x4d 0x03 / 0x03 0x0 / 0x0
NOTE: When you set MPLL&UPLL values simultaneously, set MPLL value first and then UPLL value.
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X
CLOCK & POWER MANAGEMENT
PLL VALUE SELECTION TABLE It is not easy to find a proper PLL value. So, We recommend referring to the following PLL value recommendation table. Input Frequency 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz Output Frequency 48.00 MHz 96.00 MHz
(Note) (Note)
MDIV 56(0X38) 56(0x38) 246(0xf6) 199(0xc7) 150(0x96) 199(0xc7) 150(0x96) 212(0xd4) 119(0x77) 71(0x47) 246(0xf6) 233(0xe9) 85(0x55) 88(0x58) 246(0xf6) 135(0x87) 249(0xf9) 199(0xc7) 150(0x96) 199(0xc7) 119(0x77) 230(0xe6) 150(0x96) 86(0x56) 64(0x40) 212(0xd4) 119(0x77) 71(0x47) 126(0x7e)
PDIV 2 2 13(0xd) 9 6 8 5 7 3 1 7 6 1 1 13(0xd) 2 12(0xc) 9 6 8 4 9 5 2 1 7 3 1 3
SDIV 2 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
101.60 MHz 112.909 MHz 118.50 MHz 124.20 MHz 135.429 MHz 146.667 MHz 152.400 MHz 158.00 MHz 169.333 MHz 180.750 MHz 186.00 MHz 192.00 MHz 203.20 MHz 214.50 MHz 220.286 MHz 225.818 MHz 237.00 MHz 248.40 MHz 254.00 MHz 259.636 MHz 270.857 MHz 282.00 MHz 288.00 MHz 293.333 MHz 304.80 MHZ 316.00 MHz 321.60 MHz
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2003.09.25
CLOCK & POWER MANAGEMENT
S3C2440X
PLL VALUE SELECTION TABLE (Continued) Input Frequency 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz Output Frequency 327.429 MHz 338.667 MHz 350.00 MHz 355.50 MHz 361.50 MHz 372.00 MHz 384.00 MHz 389.143 MHz 400.00 MHz MDIV 183(0xb7) 246(0xf6) 167(0xa7) 229(0xe5) 233(0xe9) 85(0x55) 88(0x58) 219(0xdb) 92(0x5c) PDIV 5 7 4 6 6 1 1 5 1 SDIV 0 0 0 0 0 0 0 0 0
NOTE: The 48.00MHz and 96MHz output is used for UPLLCON register.
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X
CLOCK & POWER MANAGEMENT
CLOCK CONTROL REGISTER (CLKCON) Register CLKCON Address 0x4C00000C R/W R/W Description Clock generator control register Reset Value 0xFFFF0
CLKCON Camera SPI IIS IIC ADC(&Touch Screen) RTC
Bit [19] [18] [17] [16] [15] [14]
GPIO UART2 UART1 UART0 SDI PWMTIMER USB device USB host LCDC NAND Flash Controller SLEEP IDLE BIT Reserved Reserved
[13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
Description Control HCLK into Camera block. 0 = Disable, 1 = Enable Control PCLK into SPI block. 0 = Disable, 1 = Enable Control PCLK into IIS block. 0 = Disable, 1 = Enable Control PCLK into IIC block. 0 = Disable, 1 = Enable Control PCLK into ADC block. 0 = Disable, 1 = Enable Control PCLK into RTC control block. Even if this bit is cleared to 0, RTC timer is alive. 0 = Disable, 1 = Enable Control PCLK into GPIO block. 0 = Disable, 1 = Enable Control PCLK into UART2 block. 0 = Disable, 1 = Enable Control PCLK into UART1 block. 0 = Disable, 1 = Enable Control PCLK into UART0 block. 0 = Disable, 1 = Enable Control PCLK into SDI interface block. 0 = Disable, 1 = Enable Control PCLK into PWMTIMER block. 0 = Disable, 1 = Enable Control PCLK into USB device block. 0 = Disable, 1 = Enable Control HCLK into USB host block. 0 = Disable, 1 = Enable Control HCLK into LCDC block. 0 = Disable, 1 = Enable Control HCLK into NAND Flash Controller block. 0 = Disable, 1 = Enable Control SLEEP mode of S3C2440X. 0 = Disable, 1 = Transition to SLEEP mode Enter IDLE mode. This bit is not cleared automatically. 0 = Disable, 1 = Transition to IDLE mode Reserved Reserved
Initial State 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 0 0 0 0
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2003.09.25
CLOCK & POWER MANAGEMENT
S3C2440X
CLOCK SLOW CONTROL (CLKSLOW) REGISTER Register CLKSLOW Address 0x4C000010 R/W R/W Description Slow clock control register Reset Value 0x00000004
CLKSLOW UCLK_ON
Bit [7]
Description 0: UCLK ON (UPLL is also turned on and the UPLL lock time is inserted automatically.) 1: UCLK OFF (UPLL is also turned off.) Reserved 0: Turn on PLL. After PLL stabilization time (minimum 300us), SLOW_BIT can be cleared to 0. 1: Turn off PLL. PLL is turned off only when SLOW_BIT is 1.
Initial State 0
Reserved MPLL_OFF
[6] [5]
- 0
SLOW_BIT
[4]
0 : FCLK = Mpll (MPLL output) 1: SLOW mode FCLK = input clock/(2xSLOW_VAL), when SLOW_VAL>0 FCLK = input clock, when SLOW_VAL=0. Input clock = XTIpll or EXTCLK
0
Reserved SLOW_VAL
[3] [2:0]
- The divider value for the slow clock when SLOW_BIT is on.
- 0x4
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X
CLOCK & POWER MANAGEMENT
CLOCK DIVIDER CONTROL (CLKDIVN) REGISTER Register CLKDIVN Address 0x4C000014 R/W R/W Description Clock divider control register Reset Value 0x00000000
CLKDIVN DIVN_UPLL
Bit [3]
Description UCLK select register(UCLK must be 48MHz for USB) 0: UCLK = UPLL clock 1: UCLK = UPLL clock / 2 Set to 0, when UPLL clock is set as 48Mhz Set to 1. when UPLL clock is set as 96Mhz.
Initial State 0
HDIVN
[2:1]
00: HCLK has the clock same as the FCLK/1. 01: HCLK has the clock same as the FCLK/2. 10: HCLK has the clock same as the FCLK/4. 11: HCLK has the clock same as the FCLK/3.
0
PDIVN
[0]
0: PCLK has the clock same as the HCLK/1. 1: PCLK has the clock same as the HCLK/2.
0
CAMERA CLOCK DIVIDER (CAMDIVN) REGISTER Register CAMDIVN Address 0x4C000018 R/W R/W Description Camera clock divider register Reset Value 0x00000000
CAMDIVN CAMCLK_SEL CAMCLK_DIV
Bit [4] [3:0]
Description 0:Use CAMCLK with UPLL output(CAMCLK=UPLL output). 1:CAMCLK is divided by CAMCLK_DIV value. CAMCLK divide factor setting register(0 - 15). Camera clock = UPLL / [(CAMCLK_DIV +1)x2]. This bit is valid when CAMCLK_SEL=1.
Initial State 0 0
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2003.09.25
S3C2440X RISC MICROPROCESSOR
DMA
8
DMA
OVERVIEW
The S3C2440X supports four-channel DMA controller that is located between the system bus and the peripheral bus. Each channel of DMA controller can perform data movements between devices in the system bus and/or peripheral bus with no restrictions. In other words, each channel can handle the following four cases: 1) both source and destination are in the system bus, 2) the source is in the system bus while the destination is in the peripheral bus, 3) the source is in the peripheral bus while the destination is in the system bus, and 4) both source and destination are in the peripheral bus. The main advantage of the DMA is that it can transfer the data without CPU intervention. The operation of DMA can be initiated by software, or requests from internal peripherals or external request pins.
8-1
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
DMA
S3C2440X RISC MICROPROCESSOR
DMA REQUEST SOURCES
Each channel of the DMA controller can select one of DMA request source among four DMA sources if H/W DMA request mode is selected by DCON register. (Note that if S/W request mode is selected, this DMA request sources have no meaning at all.) Table 8-1 shows four DMA sources for each channel.
Source0 Ch-0 Ch-1 Ch-2 Ch-3
nXDREQ0 nXDREQ1 I2SSDO UART2
Source1
UART0 UART1 I2SSDI SDI
Source2
SDI I2SSDI SDI SPI1
Source3
Timer SPI0 Timer Timer
Source4
USB device EP1 USB device EP2 USB device EP3 USB device EP4
Table 8-1. DMA Request Sources for Each Channel Here, nXDREQ0 and nXDREQ1 represent two external sources(External Devices), and I2SSDO and I2SSDI represent IIS transmitting and receiving, respectively.
DMA OPERATION
DMA uses three-state FSM (Finite State Machine) for its operation, which is described in the three following steps: State-1. State-2. State-3. As an initial state, the DMA waits for a DMA request. If it comes, it goes to state-2. At this state, DMA ACK and INT REQ are 0. In this state, DMA ACK becomes 1 and the counter (CURR_TC) is loaded from DCON[19:0] register. Note that the DMA ACK remains 1 until it is cleared later. In this state, sub-FSM handling the atomic operation of DMA is initiated. The sub-FSM reads the data from the source address and then writes it to destination address. In this operation, data size and transfer size (single or burst) are considered. This operation is repeated until the counter (CURR_TC) becomes 0 in Whole service mode, while performed only once in Single service mode. The main FSM (this FSM) counts down the CURR_TC when the sub-FSM finishes each of atomic operation. In addition, this main FSM asserts the INT REQ signal when CURR_TC becomes 0 and the interrupt setting of DCON[29] register is set to 1. In addition, it clears DMA ACK if one of the following conditions is met. 1) CURR_TC becomes 0 in the Whole service mode 2) Atomic operation finishes in the Single service mode.
Note that in the Single service mode, these three states of main FSM are performed and then stops, and waits for another DMA REQ. And if DMA REQ comes in, all three states are repeated. Therefore, DMA ACK is asserted and then deasserted for each atomic transfer. In contrast, in the Whole service mode, main FSM waits at state-3 until CURR_TC becomes 0. Therefore, DMA ACK is asserted during all the transfers and then deasserted when TC reaches 0. However, INT REQ is asserted only if CURR_TC becomes 0 regardless of the service mode (Single service mode or Whole service mode).
8-2
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
DMA
EXTERNAL DMA DREQ/DACK PROTOCOL There are three types of external DMA request/acknowledge protocols (Single service Demand, Single service Handshake and Whole service Handshake mode). Each type defines how the signals like DMA request and acknowledge are related to these protocols.
Basic DMA Timing The DMA service means performing paired Reads and Writes cycles during DMA operation, which can make one DMA operation. Figure 8-1 shows the basic Timing in the DMA operation of the S3C2440X. The setup time and the delay time of XnXDREQ and XnXDACK are the same in all the modes. If the completion of XnXDREQ meets its setup time, it is synchronized twice and then XnXDACK is asserted. After assertion of XnXDACK, DMA requests the bus and if it gets the bus it performs its operations. XnXDACK is deasserted when DMA operation is completed.
XSCLK
9.3ns Setup 9.3ns Setup Min. 2XSCLK 6.6ns Delay
XnXDREQ
XnXDACK
Min. 3XSCLK 6.8ns Delay
Read Write
Figure 8-1. Basic DMA Timing Diagram
8-3
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
DMA
S3C2440X RISC MICROPROCESSOR
Demand/Handshake Mode Comparison Demand and Handshake modes are related to the protocol between XnXDREQ and XnXDACK. Figure 8-2 shows the differences between the two modes. At the end of one transfer (Single/Burst transfer), DMA checks the state of double-synched XnXDREQ. Demand mode If XnXDREQ remains asserted, the next transfer starts immediately. Otherwise it waits for XnXDREQ to be asserted.
Handshake mode If XnXDREQ is deasserted, DMA deasserts XnXDACK in 2cycles. Otherwise it waits until XnXDREQ is deasserted. Caution: XnXDREQ has to be asserted (low) only after the deassertion (high) of XnXDACK.
XSCLK Demand Mode XnXDREQ
2cycles 1st Transfer 2nd Transfer Write Read BUS Acquisiton Actual Transfer Write
XnXDACK
Double synch Read
Handshake Mode XnXDREQ
Read
Write 2cycles Double synch 2cycles
XnXDACK
Figure 8-2. Demand/Handshake Mode Comparison
8-4
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
DMA
Transfer Size
There are two different transfer sizes; unit and Burst 4. DMA holds the bus firmly during the transfer of the chunk of data. Thus, other bus masters cannot get the bus.
Burst 4 Transfer Size There will be four sequential Reads and Writes respectively are performed in the Burst 4 Transfer. * Note: Unit Transfer size: One read and one write are performed.
XSCLK
XnXDREQ
XnXDACK
Double synch 3 cycles
Read
Read
Read
Read
Write
Write
Write
Write
Figure 8-3. Burst 4 Transfer Size
8-5
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2003.09.25
DMA
S3C2440X RISC MICROPROCESSOR
EXAMPLES
Single service in Demand Mode with Unit Transfer Size The assertion of XnXDREQ will be a need for every unit transfer (Single service mode). The operation continues while the XnXDREQ is asserted (Demand mode), and one pair of Read and Write (Single transfer size) is performed.
XSCLK
XnXDREQ
XnXDACK
Double synch
Read
Write
Read
Write
Figure 8-4. Single service in Demand Mode with Unit Transfer Size
Single service in Handshake Mode with Unit Transfer Size
XSCLK
XnXDREQ
XnXDACK
Double synch
Read
Write
2cycles
Read
Write
Figure 8-5. Single service in Handshake Mode with Unit Transfer Size
Whole service in Handshake Mode with Unit Transfer Size
XSCLK
XnXDREQ
XnXDACK
Double synch 3 cycles
Read
Write
2cycles
Read
Write
2cycles
Read
Write
Figure 8-6. Whole service in Handshake Mode with Unit Transfer Size
8-6
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
DMA
DMA SPECIAL REGISTERS
Each DMA channel has nine control registers (36 in total since there are four channels for DMA controller). Six of the control registers control the DMA transfer, and other three ones monitor the status of DMA controller. The details of those registers are as follows.
DMA INITIAL SOURCE (DISRC) REGISTER Register DISRC0 DISRC1 DISRC2 DISRC3 Address 0x4B000000 0x4B000040 0x4B000080 0x4B0000C0 R/W R/W R/W R/W R/W Description DMA 0 initial source register DMA 1 initial source register DMA 2 initial source register DMA 3 initial source register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000
DISRCn S_ADDR
Bit [30:0]
Description Base address (start address) of source data to transfer. This bit value will be loaded into CURR_SRC only if the CURR_SRC is 0 and the DMA ACK is 1.
Initial State 0x00000000
DMA INITIAL SOURCE CONTROL (DISRCC) REGISTER Register DISRCC0 DISRCC1 DISRCC2 DISRCC3 Address 0x4B000004 0x4B000044 0x4B000084 0x4B0000C4 R/W R/W R/W R/W R/W Description DMA 0 initial source control register DMA 1 initial source control register DMA 2 initial source control register DMA 3 initial source control register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000
DISRCCn LOC
Bit [1]
Description Bit 1 is used to select the location of source. 0: the source is in the system bus (AHB). 1: the source is in the peripheral bus (APB).
Initial State 0
INC
[0]
Bit 0 is used to select the address increment. 0 = Increment 1= Fixed If it is 0, the address is increased by its data size after each transfer in burst and single transfer mode. If it is 1, the address is not changed after the transfer. (In the burst mode, address is increased during the burst transfer, but the address is recovered to its first value after the transfer.)
0
8-7
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2003.09.25
DMA
S3C2440X RISC MICROPROCESSOR
DMA INITIAL DESTINATION (DIDST) REGISTER Register DIDST0 DIDST1 DIDST2 DIDST3 Address 0x4B000008 0x4B000048 0x4B000088 0x4B0000B8 R/W R/W R/W R/W R/W Description DMA 0 initial destination register DMA 1 initial destination register DMA 2 initial destination register DMA 3 initial destination register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000
DIDSTn D_ADDR
Bit [30:0]
Description Base address (start address) of destination for the transfer. This bit value will be loaded into CURR_SRC only if the CURR_DST is 0 and the DMA ACK is 1.
Initial State 0x00000000
DMA INITIAL DESTINATION CONTROL (DIDSTC) REGISTER Register DIDSTC0 DIDSTC1 DIDSTC2 DIDSTC3 Address 0x4B00000C 0x4B00004C 0x4B00008C 0x4B0000CC R/W R/W R/W R/W R/W Description DMA 0 initial destination control register DMA 1 initial destination control register DMA 2 initial destination control register DMA 3 initial destination control register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000
DIDSTCn CHK_INT
Bit [2]
Description Select interrupt occurrence time when auto reload is setting. 0 : Interrupt will occur when TC reaches 0. 1 : Interrupt will occur after autoreload is performed.
Initial State 0
LOC
[1]
Bit 1 is used to select the location of destination. 0: the destination is in the system bus (AHB). 1: the destination is in the peripheral bus (APB).
0
INC
[0]
Bit 0 is used to select the address increment. 0 = Increment 1= Fixed If it is 0, the address is increased by its data size after each transfer in burst and single transfer mode. If it is 1, the address is not changed after the transfer. (In the burst mode, address is increased during the burst transfer, but the address is recovered to its first value after the transfer.)
0
8-8
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S3C2440X RISC MICROPROCESSOR
DMA
DMA CONTROL (DCON) REGISTER Register DCON0 DCON1 DCON2 DCON3 Address 0x4B000010 0x4B000050 0x4B000090 0x4B0000D0 R/W R/W R/W R/W R/W Description DMA 0 control register DMA 1 control register DMA 2 control register DMA 3 control register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000
DCONn DMD_HS
Bit [31]
Description Select one between Demand mode and Handshake mode. 0: Demand mode will be selected. 1: Handshake mode will be selected. In both modes, DMA controller starts its transfer and asserts DACK for a given asserted DREQ. The difference between the two modes is whether it waits for the deasserted DACK or not. In the Handshake mode, DMA controller waits for the deasserted DREQ before starting a new transfer. If it finds the deasserted DREQ, it deasserts DACK and waits for another asserted DREQ. In contrast, in the Demand mode, DMA controller does not wait until the DREQ is deasserted. It just deasserts DACK and then starts another transfer if DREQ is asserted. We recommend using Handshake mode for external DMA request sources to prevent unintended starts of new transfers.
Initial State 0
SYNC
[30]
Select DREQ/DACK synchronization. 0: DREQ and DACK are synchronized to PCLK (APB clock). 1: DREQ and DACK are synchronized to HCLK (AHB clock). Therefore, for devices attached to AHB system bus, this bit has to be set to 1, while for those attached to APB system, it should be set to 0. For the devices attached to external systems, the user should select this bit depending on which the external system is synchronized with between AHB system and APB system.
0
INT
[29]
Enable/Disable the interrupt setting for CURR_TC (terminal count) 0: CURR_TC interrupt is disabled. The user has to view the transfer count in the status register (i.e. polling). 1: interrupt request is generated when all the transfer is done (i.e. CURR_TC becomes 0).
0
TSZ
[28]
Select the transfer size of an atomic transfer (i.e. transfer performed each time DMA owns the bus before releasing the bus). 0: a unit transfer is performed. 1: a burst transfer of length four is performed.
0
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2003.09.25
DMA
S3C2440X RISC MICROPROCESSOR
DCONn SERVMODE
Bit [27]
Description Select the service mode between Single service mode and Whole service mode. 0: Single service mode is selected in which after each atomic transfer (single or burst of length four) DMA stops and waits for another DMA request. 1: Whole service mode is selected in which one request gets atomic transfers to be repeated until the transfer count reaches to 0. In this mode, additional request are not required. Note that even in the Whole service mode, DMA releases the bus after each atomic transfer and then tries to re-get the bus to prevent starving of other bus masters.
Initial State 0
HWSRCSEL
[26:24]
Select DMA request source for each DMA.
DCON0: 000:nXDREQ0 001:UART0 DCON1: 000:nXDREQ1 001:UART1 DCON2: 000:I2SSDO 001:I2SSDI DCON3: 000:UART2 001:SDI 010:SDI 010:I2SSDI 010:SDI 010:SPI 011:Timer 011:SPI 011:Timer 011:Timer 100:USB device EP1 100:USB device EP2 100:USB device EP3 100:USB device EP4
00
These bits control the 4-1 MUX to select the DMA request source of each DMA. These bits have meanings only if H/W request mode is selected by DCONn[23]. SWHW_SEL [23] Select the DMA source between software (S/W request mode) and hardware (H/W request mode). 0: S/W request mode is selected and DMA is triggered by setting SW_TRIG bit of DMASKTRIG control register. 1: DMA source selected by bit[26:24] triggers the DMA operation. RELOAD [22] Set the reload on/off option. 0: auto reload is performed when a current value of transfer count becomes 0 (i.e. all the required transfers are performed). 1: DMA channel (DMA REQ) is turned off when a current value of transfer count becomes 0. The channel on/off bit (DMASKTRIGn[1]) is set to 0 (DREQ off) to prevent unintended further start of new DMA operation. DSZ [21:20] Data size to be transferred. 00 = Byte 10 = Word TC [19:0] 01 = Half word 11 = reserved 00000 00 0 0
Initial transfer count (or transfer beat). Note that the actual number of bytes that are transferred is computed by the following equation: DSZ x TSZ x TC. Where, DSZ, TSZ (1 or 4), and TC represent data size (DCONn[21:20]), transfer size (DCONn[28]), and initial transfer count, respectively. This value will be loaded into CURR_TC only if the CURR_TC is 0 and the DMA ACK is 1.
8-10
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S3C2440X RISC MICROPROCESSOR
DMA
DMA STATUS (DSTAT) REGISTER Register DSTAT0 DSTAT1 DSTAT2 DSTAT3 Address 0x4B000014 0x4B000054 0x4B000094 0x4B0000D4 R/W R R R R Description DMA 0 count register DMA 1 count register DMA 2 count register DMA 3 count register Reset Value 000000h 000000h 000000h 000000h
DSTATn STAT
Bit [21:20] Status of this DMA controller.
Description 00: Indicates that DMA controller is ready for another DMA request. 01: Indicates that DMA controller is busy for transfers.
Initial State 00b
CURR_TC
[19:0]
Current value of transfer count. Note that transfer count is initially set to the value of DCONn[19:0] register and decreased by one at the end of every atomic transfer.
00000h
8-11
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
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DMA
S3C2440X RISC MICROPROCESSOR
DMA CURRENT SOURCE (DCSRC) REGISTER Register DCSRC0 DCSRC1 DCSRC2 DCSRC3 Address 0x4B000018 0x4B000058 0x4B000098 0x4B0000D8 R/W R R R R Description DMA 0 current Source Register DMA 1 current Source Register DMA 2 current Source Register DMA 3 current Source Register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000
DCSRCn CURR_SRC
Bit [30:0]
Description Current source address for DMAn
Initial State 0x00000000
CURRENT DESTINATION (DCDST) REGISTER Register DCDST0 DCDST1 DCDST2 DCDST3 Address 0x4B00001C 0x4B00005C 0x4B00009C 0x4B0000DC R/W R R R R Description DMA 0 current destination register DMA 1 current destination register DMA 2 current destination register DMA 3 current destination register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000
DCDSTn CURR_DST
Bit [30:0]
Description Current destination address for DMAn
Initial State 0x00000000
8-12
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S3C2440X RISC MICROPROCESSOR
DMA
DMA MASK TRIGGER (DMASKTRIG) REGISTER Register DMASKTRIG0 DMASKTRIG1 DMASKTRIG2 DMASKTRIG3 Address 0x4B000020 0x4B000060 0x4B0000A0 0x4B0000E0 R/W R/W R/W R/W R/W Description DMA 0 mask trigger register DMA 1 mask trigger register DMA 2 mask trigger register DMA 3 mask trigger register Reset Value 000 000 000 000
DMASKTRIGn STOP
Bit [2] Stop the DMA operation.
Description 1: DMA stops as soon as the current atomic transfer ends. If there is no current running atomic transfer, DMA stops immediately. The CURR_TC, CURR_SRC, and CURR_DST will be 0. Note: Due to possible current atomic transfer, "stop" operation may take several cycles. The finish of the operation (i.e. actual stop time) can be detected as soon as the channel on/off bit (DMASKTRIGn[1]) is set to off. This stop is "actual stop".
Initial State 0
ON_OFF
[1]
DMA channel on/off bit. 0: DMA channel is turned off. (DMA request to this channel is ignored.) 1: DMA channel is turned on and the DMA request is handled. This bit is automatically set to off if we set the DCONn[22] bit to "no auto reload" and/or STOP bit of DMASKTRIGn to "stop". Note that when DCON[22] bit is "no auto reload", this bit becomes 0 when CURR_TC reaches 0. If the STOP bit is 1, this bit becomes 0 as soon as the current atomic transfer is completed. Note. This bit should not be changed manually during DMA operations (i.e. this has to be changed only by using DCON[22] or STOP bit).
0
SW_TRIG
[0]
Trigger the DMA channel in S/W request mode. 1: it requests a DMA operation to this controller.
0
Note that this trigger gets effective after S/W request mode has to be selected (DCONn[23]) and channel ON_OFF bit has to be set to 1 (channel on). When DMA operation starts, this bit is cleared automatically. Note: You are allowed to change the values of DISRC register, DIDST registers, and TC field of DCON register. Those changes take effect only after the finish of current transfer (i.e. when CURR_TC becomes 0). On the other hand, any change made to other registers and/or fields takes immediate effect. Therefore, be careful in changing those registers and fields.
8-13
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2003.09.25
DMA
S3C2440X RISC MICROPROCESSOR
NOTES
8-14
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2003.09.25
S3C2440X RISC MICROPROCESSOR
I/O PORTS
I/O PORTS
OVERVIEW
S3C2440X has 130 multi-functional input/output port pins. There are eight ports: - Port A(GPA): 25-output port - Port B(GPB): 11-input/out port - Port C(GPC): 16-input/output port - Port D(GPD): 16-input/output port - Port E(GPE): 16-input/output port - Port F(GPF): 8-input/output port - Port G(GPG): 16-input/output port - Port H(GPH): 9-input/output port - Port J(GPJ): 13-input/output port Each port can be easily configured by software to meet various system configurations and design requirements. You have to define which function of each pin is used before starting the main program. If a pin is not used for multiplexed functions, the pin can be configured as I/O ports. Initial pin states are configured seamlessly to avoid problems.
9-1
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2003.09.25
I/O PORTS
S3C2440X RISC MICROPROCESSOR
Table 9-1. S3C2440X Port Configuration(Sheet 1 of 5) Port A GPA22 GPA21 GPA20 GPA19 GPA18 GPA17 GPA16 GPA15 GPA14 GPA13 GPA12 GPA11 GPA10 GPA9 GPA8 GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0 Output only Output only Output only Output only Output only Output only Output only Output only Output only Output only Output only Output only Output only Output only Output only Output only Output only Output only Output only Output only Output only Output only Output only Selectable Pin Functions nFCE nRSTOUT nFRE nFWE ALE CLE nGCS5 nGCS4 nGCS3 nGCS2 nGCS1 ADDR26 ADDR25 ADDR24 ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16 ADDR0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
9-2
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2003.09.25
S3C2440X RISC MICROPROCESSOR
I/O PORTS
Table 9-1. S3C2440X Port Configuration(Sheet 2 of 5) Port B GPB10 GPB9 GPB8 GPB7 GPB6 GPB5 GPB4 GPB3 GPB2 GPB1 GPB0 Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Selectable Pin Functions nXDREQ0 nXDACK0 nXDREQ1 nXDACK1 nXBREQ nXBACK TCLK0 TOUT3 TOUT2 TOUT1 TOUT0 - - - - - - - - - - - - - - - - - - - - - -
Port C GPC15 GPC14 GPC13 GPC12 GPC11 GPC10 GPC9 GPC8 GPC7 GPC6 GPC5 GPC4 GPC3 GPC2 GPC1 GPC0 Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output
Selectable Pin Functions VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 LCD_LPCREVB LCD_LPCREV LCD_LPCOE VM VFRAME VLINE VCLK LEND - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
9-3
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
I/O PORTS
S3C2440X RISC MICROPROCESSOR
Table 9-1. S3C2440X Port Configuration(Sheet 3 of 5) Port D GPD15 GPD14 GPD13 GPD12 GPD11 GPD10 GPD9 GPD8 GPD7 GPD6 GPD5 GPD4 GPD3 GPD2 GPD1 GPD0 Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Selectable Pin Functions VD23 VD22 VD21 VD20 VD19 VD18 VD17 VD16 VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8 nSS0 nSS1 - - - SPICLK1 SPIMOSI1 SPIMISO1 - - - - - - - - - - - - - - - - - - - - - - - -
Port E GPE15 GPE14 GPE13 GPE12 GPE11 GPE10 GPE9 GPE8 GPE7 GPE6 GPE5 GPE4 GPE3 GPE2 GPE1 GPE0 Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output
Selectable Pin Functions IICSDA IICSCL SPICLK0 SPIMOSI0 SPIMISO0 SDDAT3 SDDAT2 SDDAT1 SDDAT0 SDCMD SDCLK I2SSDO I2SSDI CDCLK I2SSCLK I2SLRCK - - - - - - - - - - - I2SSDI nSS0 - - - - - - - - - - - - - - - - - - -
9-4
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
I/O PORTS
Table 9-1. S3C2440X Port Configuration(Sheet 4 of 5) Port F GPF7 GPF6 GPF5 GPF4 GPF3 GPF2 GPF1 GPF0 Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Selectable Pin Functions EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0 - - - - - - - - - -
Port G GPG15 GPG14 GPG13 GPG12 GPG11 GPG10 GPG9 GPG8 GPG7 GPG6 GPG5 GPG4 GPG3 GPG2 GPG1 GPG0 Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output
Selectable Pin Functions EINT23 EINT22 EINT21 EINT20 EINT19 EINT18 EINT17 EINT16 EINT15 EINT14 EINT13 EINT12 EINT11 EINT10 EINT9 EINT8 - - - - TCLK1 nCTS1 nRTS1 - SPICLK1 SPIMOSI1 SPIMISO1 LCD_PWREN nSS1 nSS0 - - - - - - - - - - - - - - - - - -
9-5
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
I/O PORTS
S3C2440X RISC MICROPROCESSOR
Table 9-1. S3C2440X Port Configuration(Sheet 5 of 5) Port H GPH10 GPH9 GPH8 GPH7 GPH6 GPH5 GPH4 GPH3 GPH2 GPH1 GPH0 Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Selectable Pin Functions CLKOUT1 CLKOUT0 UCLK RXD2 TXD2 RXD1 TXD1 RXD0 TXD0 nRTS0 nCTS0 - - - nCTS1 nRTS1 - - - - - - - - - - - - - - - - -
Port J GPJ12 GPJ11 GPJ10 GPJ9 GPJ8 GPJ7 GPJ6 GPJ5 GPJ4 GPJ3 GPJ2 GPJ1 GPJ0 Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output
Selectable Pin Functions CAMRESET CAMCLKOUT CAMHREF CAMVSYNC CMAPCLKIN CAMDATA7 CAMDATA6 CAMDATA5 CAMDATA4 CAMDATA3 CAMDATA2 CAMDATA1 CAMDATA0 - - - - - - - - - - - - - - - - - - - - - - - - - -
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2003.09.25
S3C2440X RISC MICROPROCESSOR
I/O PORTS
PORT CONTROL DESCRIPTIONS
PORT CONFIGURATION REGISTER(GPACON-GPJCON) In S3C2440X, most pins are multiplexed pins. So, It is determined which function is selected for each pins. The PnCON(port control register) determines which function is used for each pin. If PE0 - PE7 is used for the wakeup signal in power down mode, these ports must be configured in interrupt mode. PORT DATA REGISTER(GPADAT-GPJDAT) If Ports are configured as output ports, data can be written to the corresponding bit of PnDAT. If Ports are configured as input ports, the data can be read from the corresponding bit of PnDAT. PORT PULL-UP REGISTER(GPBUP-GPJUP) The port pull-up register controls the pull-up resister enable/disable of each port group. When the corresponding bit is 0, the pull-up resister of the pin is enabled. When 1, the pull-up resister is disabled. If the port pull-up register is enabled then the pull-up resisters work without pin's functional setting(input, output, DATAn, EINTn and etc) MISCELLANEOUS CONTROL REGISTER This register controls DATA port pull-up resister in Sleep mode, USB pad, and CLKOUT selection. EXTERNAL INTERRUPT CONTROL REGISTER The 24 external interrupts are requested by various signaling methods. The EXTINT register configures the signaling method among the low level trigger, high level trigger, falling edge trigger, rising edge trigger, and both edge trigger for the external interrupt request Because each external interrupt pin has a digital filter, the interrupt controller can recognize the request signal that is longer than 3 clocks. EINT[15:0] are used for wakeup sources.
9-7
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
I/O PORTS
S3C2440X RISC MICROPROCESSOR
I/O PORT CONTROL REGISTER
PORT A CONTROL REGISTERS(GPACON, GPADAT) Register GPACON GPADAT Reserved Reserved Address 0x56000000 0x56000004 0x56000008 0x5600000c R/W R/W R/W Description Configures the pins of port A The data register for port A Reserved Reserved Reset Value 0xffffff Undef. Undef Undef
GPACON GPA24 GPA23 GPA22 GPA21 GPA20 GPA19 GPA18 GPA17 GPA16 GPA15 GPA14 GPA13 GPA12 GPA11 GPA10 GPA9 GPA8 GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0
Bit [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] reserved reserved 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output
Description
1 = nFCE 1 = nRSTOUT 1 = nFRE 1 = nFWE 1 = ALE 1 = CLE 1 = nGCS[5] 1 = nGCS[4] 1 = nGCS[3] 1 = nGCS[2] 1 = nGCS[1] 1 = ADDR26 1 = ADDR25 1 = ADDR24 1 = ADDR23 1 = ADDR22 1 = ADDR21 1 = ADDR20 1 = ADDR19 1 = ADDR18 1 = ADDR17 1 = ADDR16 1 = ADDR0
9-8
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
I/O PORTS
GPADAT GPA[24:0]
Bit [24:0]
Description When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
nRSTOUT = nRESET & nWDTRST & SW_RESET
9-9
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
I/O PORTS
S3C2440X RISC MICROPROCESSOR
PORT B CONTROL REGISTERS(GPBCON, GPBDAT, GPBUP) Register GPBCON GPBDAT GPBUP Reserved Address 0x56000010 0x56000014 0x56000018 0x5600001c R/W R/W R/W R/W Description Configures the pins of port B The data register for port B pull-up disable register for port B Reset Value 0x0 Undef. 0x0
PBCON GPB10 GPB9 GPB8 GPB7 GPB6 GPB5 GPB4 GPB3 GPB2 GPB1 GPB0
Bit [21:20] [19:18] [17:16] [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 00 = Input 10 = nXDREQ0 00 = Input 10 = nXDACK0 00 = Input 10 = nXDREQ1 00 = Input 10 = nXDACK1 00 = Input 10 = nXBREQ 00 = Input 10 = nXBACK 00 = Input 10 = TCLK [0] 00 = Input 10 = TOUT3 00 = Input 10 = TOUT2 00 = Input 10 = TOUT1 00 = Input 10 = TOUT0
Description 01 = Output 11 = reserved 01 = Output 11 = reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = reserved 01 = Output 11 = reserved 01 = Output 11 = reserved 01 = Output 11 = reserved 01 = Output 11 = reserved] 01 = Output 11 = reserved 01 = Output 11 = reserved
GPBDAT GPB[10:0]
Bit [10:0]
Description When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
GPBUP GPB[10:0]
Bit [10:0]
Description 0: the pull up function attached to to the corresponding port pin is enabled. 1: the pull up function is disabled.
9-10
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
I/O PORTS
PORT C CONTROL REGISTERS(GPCCON, GPCDAT, GPCUP) Register GPCCON GPCDAT GPCUP Reserved Address 0x56000020 0x56000024 0x56000028 0x5600002c R/W R/W R/W R/W Description Configures the pins of port C The data register for port C pull-up disable register for port C Reset Value 0x0 Undef. 0x0 -
GPCCON GPC15 GPC14 GPC13 GPC12 GPC11 GPC10 GPC9 GPC8 GPC7 GPC6 GPC5 GPC4 GPC3 GPC2 GPC1 GPC0
Bit [31:30] [29:28] [27:26] [25:24] [23:22] [21:20] [19:18] [17:16] [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 00 = Input 10 = VD[7] 00 = Input 10 = VD[6] 00 = Input 10 = VD[5] 00 = Input 10 = VD[4] 00 = Input 10 = VD[3] 00 = Input 10 = VD[2] 00 = Input 10 = VD[1] 00 = Input 10 = VD[0] 00 = Input 10 = LCD_LPCREVB 00 = Input 10 = LCD_LPCREV 00 = Input 10 = LCD_LPCOE 00 = Input 10 = VM 00 = Input 10 = VFRAME 00 = Input 10 = VLINE 00 = Input 10 = VCLK 00 = Input 10 = LEND
Description 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = I2SSDI 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved
9-11
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
I/O PORTS
S3C2440X RISC MICROPROCESSOR
GPCDAT GPC[15:0]
Bit [15:0]
Description When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
GPCUP GPC[15:0]
Bit [15:0]
Description 0: the pull up function attached to to the corresponding port pin is enabled. 1: the pull up function is disabled.
9-12
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
I/O PORTS
PORT D CONTROL REGISTERS(GPDCON, GPDDAT, GPDUP) Register GPDCON GPDDAT GPDUP Reserved Address 0x56000030 0x56000034 0x56000038 0x5600003c R/W R/W R/W R/W Description Configures the pins of port D The data register for port D pull-up disable register for port D Reset Value 0x0 Undef. 0xf000
GPDCON GPD15 GPD14 GPD13 GPD12 GPD11 GPD10 GPD9 GPD8 GPD7 GPD6 GPD5 GPD4 GPD3 GPD2 GPD1 GPD0
Bit [31:30] [29:28] [27:26] [25:24] [23:22] [21:20] [19:18] [17:16] [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 00 = Input 10 = VD[23] 00 = Input 10 = VD[22] 00 = Input 10 = VD[21] 00 = Input 10 = VD[20] 00 = Input 10 = VD[19] 00 = Input 10 = VD[18] 00 = Input 10 = VD[17] 00 = Input 10 = VD[16] 00 = Input 10 = VD[15] 00 = Input 10 = VD[14] 00 = Input 10 = VD[13] 00 = Input 10 = VD[12] 00 = Input 10 = VD[11] 00 = Input 10 = VD[10] 00 = Input 10 = VD[9] 00 = Input 10 = VD[8]
Description 01 = Output 11 = nSS0 01 = Output 11 = nSS1 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = SPICLK1 01 = Output 11 = SPIMOSI1 01 = Output 11 = SPIMISO1 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved
9-13
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
I/O PORTS
S3C2440X RISC MICROPROCESSOR
GPDDAT GPD[15:0]
Bit [15:0]
Description When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
GPDUP GPD[15:0]
Bit [15:0]
Description 0: the pull up function attached to to the corresponding port pin is enabled. 1: the pull up function is disabled.
9-14
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
I/O PORTS
PORT E CONTROL REGISTERS(GPECON, GPEDAT, GPEUP) Register GPECON GPEDAT GPEUP Reserved Address 0x56000040 0x56000044 0x56000048 0x5600004c R/W R/W R/W R/W Description Configures the pins of port E The data register for port E pull-up disable register for port E Reset Value 0x0 Undef. 0x0000 -
GPECON GPE15
Bit [31:30]
Description 00 = Input 01 = Output 10 = IICSDA 11 = Reserved This pad is open-drain, There is no Pull-up option. 00 = Input 01 = Output 10 = IICSCL 11 = Reserved This pad is open-drain, There is no Pull-up option. 00 = Input 10 = SPICLK0 00 = Input 10 = SPIMOSI0 00 = Input 10 = SPIMISO0 00 = Input 10 = SDDAT3 00 = Input 10 = SDDAT2 00 = Input 10 = SDDAT1 00 = Input 10 = SDDAT0 00 = Input 10 = SDCMD 00 = Input 10 = SDCLK 00 = Input 10 = I2SDO 00 = Input 10 = I2SDI 00 = Input 10 = CDCLK 00 = Input 10 = I2SSCLK 00 = Input 10 = I2SLRCK 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = I2SSDI 01 = Output 11 = nSS0 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved
GPE14
[29:28]
GPE13 GPE12 GPE11 GPE10 GPE9 GPE8 GPE7 GPE6 GPE5 GPE4 GPE3 GPE2 GPE1 GPE0
[27:26] [25:24] [23:22] [21:20] [19:18] [17:16] [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0]
9-15
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
I/O PORTS
S3C2440X RISC MICROPROCESSOR
. GPEDAT GPE[15:0] Bit [15:0] Description When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit. When the port is configured as a functional pin, the undefined value will be read.
GPEUP GPE[13:0]
Bit [13:0]
Description 0: the pull up function attached to to the corresponding port pin is enabled. 1: the pull up function is disabled.
9-16
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
I/O PORTS
PORT F CONTROL REGISTERS(GPFCON, GPFDAT) If GPF0 - GPF7 will be used for wake-up signals at power down mode, the ports will be set in interrupt mode. Register GPFCON GPFDAT GPFUP Reserved Address 0x56000050 0x56000054 0x56000058 0x5600005c R/W R/W R/W R/W Description Configures the pins of port F The data register for port F pull-up disable register for port F Reset Value 0x0 Undef. 0x000
GPFCON GPF7 GPF6 GPF5 GPF4 GPF3 GPF2 GPF1 GPF0
Bit [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 00 = Input 10 = EINT[7] 00 = Input 10 = EINT[6] 00 = Input 10 = EINT[5] 00 = Input 10 = EINT[4] 00 = Input 10 = EINT[3] 00 = Input 10 = EINT2] 00 = Input 10 = EINT[1] 00 = Input 10 = EINT[0]
Description 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved
GPFDAT GPF[7:0]
Bit [7:0]
Description When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
GPFUP GPF[7:0]
Bit [7:0]
Description 0: the pull up function attached to to the corresponding port pin is enabled. 1: the pull up function is disabled.
9-17
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
I/O PORTS
S3C2440X RISC MICROPROCESSOR
PORT G CONTROL REGISTERS(GPGCON, GPGDAT) If GPG0 - GPGF7 will be used for wake-up signals at power down mode, the ports will be set in interrupt mode. Register GPGCON GPGDAT GPGUP Reserved Address 0x56000060 0x56000064 0x56000068 0x5600006c R/W R/W R/W R/W Description Configures the pins of port G The data register for port G pull-up disable register for port G Reset Value 0x0 Undef. 0xfc00 -
GPGCON GPG15* GPG14* GPG13* GPG12 GPG11 GPG10 GPG9 GPG8 GPG7 GPG6 GPG5 GPG4 GPG3 GPG2 GPG1 GPG0
Bit [31:30] [29:28] [27:26] [25:24] [23:22] [21:20] [19:18] [17:16] [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 00 = Input 10 = EINT[23] 00 = Input 10 = EINT[22] 00 = Input 10 = EINT[21] 00 = Input 10 = EINT[20] 00 = Input 10 = EINT[19] 00 = Input 10 = EINT[18] 00 = Input 10 = EINT[17] 00 = Input 10 = EINT[16] 00 = Input 10 = EINT[15] 00 = Input 10 = EINT[14] 00 = Input 10 = EINT[13] 00 = Input 10 = EINT[12] 00 = Input 10 = EINT[11] 00 = Input 10 = EINT[10] 00 = Input 10 = EINT[9]
Description 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = TCLK[1] 01 = Output 11 = nCTS1 01 = Output 11 = nRTS1 01 = Output 11 = Reserved 01 = Output 11 = SPICLK1 01 = Output 11 = SPIMOSI1 01 = Output 11 = SPIMISO1 01 = Output 11 = LCD_PWRDN 01 = Output 11 = nSS1 01 = Output 11 = nSS0 01 = Output 11 = Reserved 01 = Output 11 = Reserved
00 = Input 10 = EINT[8] NOTE: GPG[15:13] must be selected as Input in Nand-booting mode.
9-18
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
I/O PORTS
GPGDAT GPG[15:0]
Bit [15:0]
Description When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
GPGUP GPG[15:0]
Bit [15:0]
Description 0: the pull up function attached to to the corresponding port pin is enabled. 1: the pull up function is disabled.
9-19
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
I/O PORTS
S3C2440X RISC MICROPROCESSOR
PORT H CONTROL REGISTERS(GPHCON, GPHDAT) If GPF0 - GPF7 will be used for wake-up signals at power down mode, the ports will be set in interrupt mode. Register GPHCON GPHDAT GPHUP Reserved Address 0x56000070 0x56000074 0x56000078 0x5600007c R/W R/W R/W R/W Description Configures the pins of port H The data register for port H pull-up disable register for port H Reset Value 0x0 Undef. 0x000
GPHCON GPH10 GPH9 GPH8 GPH7 GPH6 GPH5 GPH4 GPH3 GPH2 GPH1 GPH0
Bit [21:20] [19:18] [17:16] [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 00 = Input 10 = CLKOUT1 00 = Input 10 = CLKOUT0 00 = Input 10 = UARTCLK 00 = Input 10 = RXD[2] 00 = Input 10 = TXD[2] 00 = Input 10 = RXD[1] 00 = Input 10 = TXD[1] 00 = Input 10 = RXD[0] 00 = Input 10 = TXD[0] 00 = Input 10 = nRTS0 00 = Input 10 = nCTS0
Description 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = nCTS1 01 = Output 11 = nRTS1 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved
9-20
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
I/O PORTS
GPHDAT GPH[10:0]
Bit [10:0]
Description When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
GPHUP GPH[10:0]
Bit [10:0]
Description 0: the pull up function attached to to the corresponding port pin is enabled. 1: the pull up function is disabled.
9-21
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
I/O PORTS
S3C2440X RISC MICROPROCESSOR
PORT J CONTROL REGISTERS(GPJCON, GPJDAT) If GPG0 - GPGF7 will be used for wake-up signals at power down mode, the ports will be set in interrupt mode. Register GPJCON GPJDAT GPJUP Reserved Address 0x560000d0 0x560000d4 0x560000d8 0x560000dc R/W R/W R/W R/W Description Configures the pins of port J The data register for port J pull-up disable register for port J Reset Value 0x0 Undef. 0x0000 -
GPJCON GPJ12 GPJ11 GPJ10 GPJ9 GPJ8 GPJ7 GPJ6 GPJ5 GPJ4 GPJ3 GPJ2 GPJ1 GPJ0
Bit [25:24] [23:22] [21:20] [19:18] [17:16] [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 00 = Input 10 = CAMRESET (O) 00 = Input 10 = CAMCLKOUT(O) 00 = Input 10 =CAMHREF (I) 00 = Input 10 = CAMVSYNC] (I) 00 = Input 10 = CAMPCLKIN] (I) 00 = Input 10 = CAMDATA[7] (I) 00 = Input 10 = CAMDATA[6] (I) 00 = Input 10 = CAMDATA[5] (I) 00 = Input 10 = CAMDATA[4] (I) 00 = Input 10 = CAMDATA[3] (I) 00 = Input 10 = CAMDATA[2] (I) 00 = Input 10 = CAMDATA[1] (I) 00 = Input 10 = CAMDATA[0] (I)
Description 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved
9-22
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
I/O PORTS
GPJDAT GPJ15:0]
Bit [12:0]
Description When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
GPJUP GPJ[12:0]
Bit [12:0]
Description 0: the pull up function attached to to the corresponding port pin is enabled. 1: the pull up function is disabled.
9-23
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
I/O PORTS
S3C2440X RISC MICROPROCESSOR
MISCELLANEOUS control register(MISCCR) In Sleep mode, the data bus(D[31:0] or D[15:0] can be set as Hi-Z and Output `0' state. But, because of the characteristics of IO pad, the data bus pull-up resisters have to be turned on or off to reduce the power consumption. D[31:0] pin pull-up resisters can be controlled by MISCCR register. Pads related USB are controlled by this register for USB host, or for USB device.
Register MISCCR
Address 0x56000080
R/W R/W
Description Miscellaneous control register
Reset Value 0x10330
MISCCR Reserved Reserved Reserved BATTFLT_INTR
Bit [24] [23] [22] [21] Reserve to 0. Reserve to 0. This bit must be 1.
Description
Reset Value 0 0 0 0
BATT_FLT Interrupt On/Off. 0: Enable 1: Disable When 1, Battery fault interrupt will be masked by hardware. BATT_FLT function On/Off. 0: Enable 1: Disable When 0, Battary fault function will be turned on. 0: Self refresh retain disable 1: Self refresh retain enable When 1, After wake-up from sleep, The self-refresh will be retained.
BATTFLT_FUNC
[20]
0
OFFREFRESH
[19]
0
nEN_SCLK1 nEN_SCLK0 nRSTCON Reserved SEL_SUSPND1 SEL_SUSPND0 CLKSEL1
[18] [17] [16] [15:14] [13] [12] [10:8]
SCLK0 output enable 0: SCLK1 = SCLK , 1: SCLK1 = 0 SCLK0 output enable 0: SCLK0 = SCLK , 1: SCLK 0 = 0 nRSTOUT' S/W reset 0: nRSTOUT = 0, 1: nRSTOUT = 1 USB Port 1 Suspend mode 0 = normal mode 1= suspend mode USB Port 0 Suspend mode 0 = normal mode 1= suspend mode 001 = Select UPLL output with CLKOUT0 pad 011 = Select HCLK with CLKOUT1 pad 100 = Select PCLK with CLKOUT1 pad 101 = Select DCLK1 with CLKOUT1 pad 11x = reserved
0 0 1 00 0 0 011
9-24
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
I/O PORTS
MISCCR Reserved CLKSEL0
Bit [7] [6:4] -
Description 001 = Select UPLL output with CLKOUT0 pad 011 = Select HCLK with CLKOUT0 pad 100 = Select PCLK with CLKOUT0 pad 101 = Select DCLK0 with CLKOUT0 pad 11x = reserved USB1 Host/Device select register. 0 = use USB1 as Device 1 = use USB1 as Host
Reset Value 0 011
SEL_USBPAD
[3]
0
Reserved SPUCR1 SPUCR0
[2] [1] [0]
Reserved 0 = DATA[31:16] port pull-up resister is enabled 1 = DATA[31:16] port pull-up resister is disabled 0 = DATA[15:0] port pull-up resister is enabled 1 = DATA[15:0] port pull-up resister is disabled
0 0 0
9-25
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
I/O PORTS
S3C2440X RISC MICROPROCESSOR
DCLK CONTROL REGISTERS(DCLKCON) Register DCLKCON Address 0x56000084 R/W R/W Description DCLK0/1 Control Register Reset Value 0x0
DCLKCON DCLK1CMP
Bit [27:24]
Description DCLK1 Compare value clock toggle value.( < DCLK1DIV) If the DCLK1DIV is n, Low level duration is( n + 1), High level duration is((DCLK1DIV + 1) -( n +1)) DCLK1 Divde value DCLK1 frequency = source clock /( DCLK1DIV + 1) Select DCLK1 source clock 0 = PCLK 1 = UCLK( USB) DCLK1 Enable 0 = DCLK1 disable 1 = DCLK1 enable
DCLK1DIV DCLK1SelCK DCLK1EN DCLK0CMP
[23:20] [17] [16] [11:8]
DCLK0 Compare value clock toggle value.( < DCLK0DIV) If the DCLK0DIV is n, Low level duration is( n + 1), High level duration is((DCLK0DIV + 1) -( n +1)) DCLK0 Divde value. DCLK0 frequency = source clock /( DCLK0DIV + 1) Select DCLK0 source clock 0 = PCLK 1 = UCLK( USB) DCLK0 Enable 0 = DCLK0 disable 1 = DCLK0 enable
DCLK0DIV DCLK0SelCK DCLK0EN
[7:4] [1] [0]
DCLKnCMP + 1 DCLKnDIV + 1
9-26
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
I/O PORTS
EXTINTn(External Interrupt Control Register n) The 8 external interrupts can be requested by various signaling methods. The EXTINT register configures the signaling method between the level trigger and edge trigger for the external interrupt request, and also configures the signal polarity. To recognize the level interrupt, the valid logic level on EXTINTn pin must be retained for 40ns at least because of the noise filter. Register EXTINT0 EXTINT1 EXTINT2 Address 0x56000088 0x5600008c 0x56000090 R/W R/W R/W R/W Description External Interrupt control Register 0 External Interrupt control Register 1 External Interrupt control Register 2 Reset Value 0x000000 0x000000 0x000000
EXTINT0 EINT7
Bit [30:28]
Description Setting the signaling method of the EINT7. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Setting the signaling method of the EINT6. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Setting the signaling method of the EINT5. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Setting the signaling method of the EINT4. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Setting the signaling method of the EINT3. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Setting the signaling method of the EINT2. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Setting the signaling method of the EINT1. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Setting the signaling method of the EINT0. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered
EINT6
[26:24]
EINT5
[22:20]
EINT4
[18:16]
EINT3
[14:12]
EINT2
[10:8]
EINT1
[6:4]
EINT0
[2:0]
9-27
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
I/O PORTS
S3C2440X RISC MICROPROCESSOR
EXTINT1 FLTEN15 EINT15
Bit [31] [30:28] Filter Enable for EINT15 0 = Filter Disable
Description 1= Filter Enable
Setting the signaling method of the EINT15. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Filter Enable for EINT14 0 = Filter Disable 1= Filter Enable
FLTEN14 EINT14
[27] [26:24]
Setting the signaling method of the EINT14. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Filter Enable for EINT13 0 = Filter Disable 1= Filter Enable
FLTEN13 EINT13
[23] [22:20]
Setting the signaling method of the EINT13. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Filter Enable for EINT12 0 = Filter Disable 1= Filter Enable
FLTEN12 EINT12
[19] [18:16]
Setting the signaling method of the EINT12. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Filter Enable for EINT11 0 = Filter Disable 1= Filter Enable
FLTEN11 EINT11
[15] [14:12]
Setting the signaling method of the EINT11. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Filter Enable for EINT10 0 = Filter Disable 1= Filter Enable
FLTEN10 EINT10
[11] [10:8]
Setting the signaling method of the EINT10. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Filter Enable for EINT9 0 = Filter Disable 1= Filter Enable
FLTEN9 EINT9
[7] [6:4]
Setting the signaling method of the EINT9. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Filter Enable for EINT8 0 = Filter Disable 1= Filter Enable
FLTEN8 EINT8
[3] [2:0]
Setting the signaling method of the EINT8. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered
9-28
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
I/O PORTS
EXTINT2 FLTEN23 EINT23
Bit [31] [30:28] Filter Enable for EINT23 0 = Filter Disable
Description 1= Filter Enable
Reset Value 0 000
Setting the signaling method of the EINT23. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Filter Enable for EINT22 0 = Filter Disable 000 = Low level 01x = Falling edge triggered 11x = Both edge triggered
FLTEN22 EINT22
[27] [26:24]
0 1= Filter Enable 000 001 = High level 10x = Rising edge triggered 0 1= Filter Enable 000 001 = High level 10x = Rising edge triggered 0 1= Filter Enable 000 001 = High level 10x = Rising edge triggered 0 1= Filter Enable 000 001 = High level 10x = Rising edge triggered 0 1= Filter Enable 000 001 = High level 10x = Rising edge triggered 0 1= Filter Enable
Setting the signaling method of the EINT22.
FLTEN21 EINT21
[23] [22:20]
Filter Enable for EINT21 0 = Filter Disable 000 = Low level 01x = Falling edge triggered 11x = Both edge triggered
Setting the signaling method of the EINT21.
FLTEN20 EINT20
[19] [18:16]
Filter Enable for EINT20 0 = Filter Disable 000 = Low level 01x = Falling edge triggered 11x = Both edge triggered
Setting the signaling method of the EINT20.
FLTEN19 EINT19
[15] [14:12]
Filter Enable for EINT19 0 = Filter Disable 000 = Low level 01x = Falling edge triggered 11x = Both edge triggered
Setting the signaling method of the EINT19.
FLTEN18 EINT18
[11] [10:8]
Filter Enable for EINT18 0 = Filter Disable 000 = Low level 01x = Falling edge triggered 11x = Both edge triggered
Setting the signaling method of the EINT18.
FLTEN17
[7]
Filter Enable for EINT17 0 = Filter Disable
9-29
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
I/O PORTS
S3C2440X RISC MICROPROCESSOR
EINT17
[6:4]
Setting the signaling method of the EINT17. 000 = Low level 01x = Falling edge triggered 11x = Both edge triggered 001 = High level 10x = Rising edge triggered
000
FLTEN16 EINT16
[3] [2:0]
Filter Enable for EINT16 0 = Filter Disable 000 = Low level 01x = Falling edge triggered 11x = Both edge triggered
0 1= Filter Enable 000 001 = High level 10x = Rising edge triggered
Setting the signaling method of the EINT16.
9-30
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
I/O PORTS
EINTFLTn(External Interrupt Filter Register n) To recognize the level interrupt, the valid logic level on EXTINTn pin must be retained for 40ns at least because of the noise filter. Register EINTFLT0 EINTFLT1 EINTFLT2 EINTFLT3 Address 0x56000094 0x56000098 0x5600009c 0x4c6000a0 R/W R/W R/W R/W R/W Description reserved reserved External Interrupt control Register 2 External Interrupt control Register 3 Reset Value 0x000000 0x000000 0x000000 0x000000
EINTFLT2 EINTFLT19 FLTCLK18 EINTFLT18 FLTCLK17 EINTFLT17 FLTCLK16 EINTFLT16
Bit [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Filtering width of EINT19
Description Filter clock of EINT18(Configured by OM) 0 = PCLK 1= EXTCLK/OSC_CLK Filtering width of EINT18 Filter clock of EINT17(Configured by OM) 0 = PCLK 1= EXTCLK/OSC_CLK Filtering width of EINT17 Filter clock of EINT16(Configured by OM) 0 = PCLK 1= EXTCLK/OSC_CLK Filtering width of EINT16
EINTFLT3 FLTCLK23 EINTFLT23 FLTCLK22 EINTFLT22 FLTCLK21 EINTFLT21 FLTCLK20 EINTFLT20
Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0]
Description Filter clock of EINT23(Configured by OM) 0 = PCLK 1= EXTCLK/OSC_CLK Filtering width of EINT23 Filter clock of EINT22(Configured by OM) 0 = PCLK 1= EXTCLK/OSC_CLK Filtering width of EINT22 Filter clock of EINT21(Configured by OM) 0 = PCLK 1= EXTCLK/OSC_CLK Filtering width of EINT21 Filter clock of EINT20(Configured by OM) 0 = PCLK 1= EXTCLK/OSC_CLK Filtering width of EINT20
9-31
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
I/O PORTS
S3C2440X RISC MICROPROCESSOR
EINTMASK(External Interrupt Mask Register) Register EINTMASK Address 0x560000a4 R/W R/W Description External interupt mask Register Reset Value 0x000fffff
EINTMASK EINT23 EINT22 EINT21 EINT20 EINT19 EINT18 EINT17 EINT16 EINT15 EINT14 EINT13 EINT12 EINT11 EINT10 EINT9 EINT8 EINT7 EINT6 EINT5 EINT4 Reserved
Bit [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3:0] 0 = enable interrupt 0 = enable interrupt 0 = enable interrupt 0 = enable interrupt 0 = enable interrupt 0 = enable interrupt 0 = enable interrupt 0 = enable interrupt 0 = enable interrupt 0 = enable interrupt 0 = enable interrupt 0 = enable interrupt 0 = enable interrupt 0 = enable interrupt 0 = enable interrupt 0 = enable interrupt 0 = enable interrupt 0 = enable interrupt 0 = enable interrupt 0 = enable interrupt Reserved
Description 1= masked 1= masked 1= masked 1= masked 1= masked 1= masked 1= masked 1= masked 1= masked 1= masked 1= masked 1= masked 1= masked 1= masked 1= masked 1= masked 1= masked 1= masked 1= masked 1= masked
9-32
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
I/O PORTS
EINTPEND(External Interrupt Pending Register) Register EINTPEND Address 0x560000a8 R/W R/W Description External interupt pending Register Reset Value 0x00
EINTPEND EINT23 EINT22 EINT21 EINT20 EINT19 EINT18 EINT17 EINT16 EINT15 EINT14 EINT13 EINT12 EINT11 EINT10 EINT9 EINT8 EINT7 EINT6
Bit [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6]
Description It is cleard by writing "1" 0 = not occur 1= occur interrupt It is cleard by writing "1" 0 = not occur 1= occur interrupt It is cleard by writing "1" 0 = not occur 1= occur interrupt It is cleard by writing "1" 0 = not occur 1= occur interrupt It is cleard by writing "1" 0 = not occur 1= occur interrupt It is cleard by writing "1" 0 = not occur 1= occur interrupt It is cleard by writing "1" 0 = not occur 1= occur interrupt It is cleard by writing "1" 0 = not occur 1= occur interrupt It is cleard by writing "1" 0 = not occur 1= occur interrupt It is cleard by writing "1" 0 = not occur 1= occur interrupt It is cleard by writing "1" 0 = not occur 1= occur interrupt It is cleard by writing "1" 0 = not occur 1= occur interrupt It is cleard by writing "1" 0 = not occur 1= occur interrupt It is cleard by writing "1" 0 = not occur 1= occur interrupt It is cleard by writing "1" 0 = not occur 1= occur interrupt It is cleard by writing "1" 0 = not occur 1= occur interrupt It is cleard by writing "1" 0 = not occur 1= occur interrupt It is cleard by writing "1" 0 = not occur 1= occur interrupt
Reset Value 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0
9-33
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
I/O PORTS
S3C2440X RISC MICROPROCESSOR
EINT5 EINT4 Reserved
[5] [4] [3:0]
It is cleard by writing "1" 0 = not occur 1= occur interrupt It is cleard by writing "1" 0 = not occur 1= occur interrupt Reserved
0
0 0000
9-34
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
I/O PORTS
GSTATUSn (General Status Registers) Register GSTATUS0 GSTATUS1 GSTATUS2 GSTATUS3 GSTATUS4 Address 0x560000ac 0x560000b0 0x560000b4 0x560000b8 0x560000bc R/W R R/W R/W R/W R/W Description External pin status Chip ID Reset Status Inform register Inform register Reset Value Not define 0x324100xx 0x1 0x0 0x0
GSTATUS0 nWAIT NCON RnB BATT_FLT
Bit [3] [2] [1] [0] Status of nWAIT pin Status of NCON pin Status of RnB pin Status of BATT_FLT pin
Description
GSTATUS1 CHIP ID
Bit [0] ID register = 0x324400-00
Description
GSTATUS2 Reserved WDTRST SLEEPRST PWRST
Bit [3] [2] [1] [0] Reserved
Description Boot is caused by Watch Dog Reset cleared by writing "1" Boot is caused by wakeup reset in sleep mode cleared by writing "1". Boot is caused by Power On Reset cleared by writing "1"
GSTATUS3 inform
Bit [31:0]
Description Inform register. This register is cleard by power on reset. Otherwise, preserve data value.
GSTATUS4 inform
Bit [31:0]
Description Inform register. This register is cleard by power on reset. Otherwise, preserve data value.
9-35
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
I/O PORTS
S3C2440X RISC MICROPROCESSOR
DSCn (Drive Strength Control) Control the Memory I/O drive strength Register DSC0 DSC1 Address 0x560000c4 0x560000c8 R/W R/W R/W Description strength control register 0 strength control register 1 Reset Value 0x0 0x0
DSC0 nEN_DSC Reserved DSC_ADR DSC_DATA3 DSC_DATA2 DSC_DATA1 DSC_DATA0
Bit [31] [30:10] [9:8] [7:6] [5:4] [3:2] [1:0]
Description enable Drive Strength Control 0: enable 1: Disable Address Bus Drive strength. 00: 12mA 01: 10mA 10: 8mA 11: 6mA
Reset Value 0 0 00 00 11: 6mA 00 11: 6mA 00 11: 6mA 00 11: 6mA
DATA[31:24] I/O Drive strength. 00: 12mA 01: 10mA 10: 8mA DATA[23:16] I/O Drive strength. 00: 12mA 01: 10mA 10: 8mA DATA[15:8] I/O Drive strength. 00: 12mA 01: 10mA 10: 8mA DATA[7:0] I/O Drive strength. 00: 12mA 01: 10mA 10: 8mA
9-36
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
I/O PORTS
DSC1 DSC_SCK1 DSC_SCK0 DSC_SCKE DSC_SDR DSC_NFC
Bit [29:28] [27:26] [25:24] [23:22] [21:20]
Description SCLK1 Drive strength. 00: 12mA 01: 10mA SCLK0 Drive strength. 00: 16mA 01: 12mA SCKE Drive strength. 00: 10mA 01: 8mA 10: 8mA 10: 8mA 10: 6mA 11: 6mA
Reset Value 00 00 11: 6mA 00 11: 4mA 00 11: 4mA 00
nSRAS/nSCAS Drive strength. 00: 10mA 01: 8mA 10: 6mA
Nand Flash Control Drive strength( nFCE, nFRE, nFWE, CLE, ALE). 00: 10mA 01: 8mA 10: 6mA 11: 4mA nBE[3:0] Drive strength. 00: 10mA 01: 8mA nWE/nOE Drive strength. 00: 10mA 01: 8mA nGCS7 Drive strength. 00: 10mA 01: 8mA nGCS6 Drive strength. 00: 10mA 01: 8mA nGCS5 Drive strength. 00: 10mA 01: 8mA nGCS4 Drive strength. 00: 10mA 01: 8mA nGCS3 Drive strength. 00: 10mA 01: 8mA nGCS2 Drive strength. 00: 10mA 01: 8mA nGCS1 Drive strength. 00: 10mA 01: 8mA nGCS0 Drive strength. 00: 10mA 01: 8mA 10: 6mA 10: 6mA 10: 6mA 10: 6mA 10: 6mA 10: 6mA 10: 6mA 10: 6mA 10: 6mA 10: 6mA 11: 4mA
DSC_BE DSC_WOE DSC_CS7 DSC_CS6 DSC_CS5 DSC_CS4 DSC_CS3 DSC_CS2 DSC_CS1 DSC_CS0
[19:18] [17:16] [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0]
00 00 11: 4mA 00 11: 4mA 00 11: 4mA 00 11: 4mA 00 11: 4mA 00 11: 4mA 00 11: 4mA 00 11: 4mA 00 11: 4mA
9-37
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
I/O PORTS
S3C2440X RISC MICROPROCESSOR
MSLCON (Memory Sleep Control Register) Select memory interface status when in SLEEP mode. Register MSLCON Address 0x560000cc R/W R/W Description Memory Sleep Control Register Reset Value 0x0
DSC0 PSC_DATA PSC_WAIT PSC_RnB PSC_NF
Bit [11] [10] [9] [8]
Description DATA[31:0] pin status in Sleep mode. 0: Hi-Z 1: Output "0". nWAIT pin status in Sleep mode. 0: Output "0" 1: Input RnB pin status in Sleep mode. 0: Output "0" 1: Input NAND Flash I/F pin status in Sleep mode( nFCE,nFRE,nFWE,ALE,CLE). 0: inactive(nFCE,nFRE,nFWE,ALE,CLE = 11100) 1: Hi-Z nSRAS, nSCAS pin status in Sleep mode. 0: inactive("1") 1: Hi-Z DQM[3:0]/nWE[3:0] pin status in Sleep mode. 0: inactive 1: Hi-Z nOE pin status in Sleep mode. 0: inactive("1") 1: Hi-Z nWE pin status in Sleep mode. 0: inactive("1") 1: Hi-Z nGCS[0] pin status in Sleep mode. 0: inactive("1") 1: Hi-Z nGCS[5:1] pin status in Sleep mode. 0: inactive("1") 1: Hi-Z nGCS[6] pin status in Sleep mode. 0: inactive("1") 1: Hi-Z nGCS[7] pin status in Sleep mode. 0: inactive("1") 1: Hi-Z
Reset Value 0 0 0 0
PSC_SDR PSC_DQM PSC_OE PSC_WE PSC_GCS0 PSC_GCS51 PSC_GCS6 PSC_GCS7
[7] [6] [5] [4] [3] [2] [1] [0]
0 0 0 0 0 0 0 0
9-38
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
PWM TIMER
10
OVERVIEW
PWM TIMER
The S3C2440X has five 16-bit timers. Timer 0, 1, 2, and 3 have Pulse Width Modulation (PWM) function. Timer 4 has an internal timer only with no output pins. The timer 0 has a dead-zone generator, which is used with a large current device. The timer 0 and 1 share an 8-bit prescaler, while the timer 2, 3 and 4 share other 8-bit prescaler. Each timer has a clock divider, which generates 5 different divided signals (1/2, 1/4, 1/8, 1/16, and TCLK). Each timer block receives its own clock signals from the clock divider, which receives the clock from the corresponding 8-bit prescaler. The 8-bit prescaler is programmable and divides the PCLK according to the loading value, which is stored in TCFG0 and TCFG1 registers. The timer count buffer register (TCNTBn) has an initial value which is loaded into the down-counter when the timer is enabled. The timer compare buffer register (TCMPBn) has an initial value which is loaded into the compare register to be compared with the down-counter value. This double buffering feature of TCNTBn and TCMPBn makes the timer generate a stable output when the frequency and duty ratio are changed. Each timer has its own 16-bit down counter, which is driven by the timer clock. When the down counter reaches zero, the timer interrupt request is generated to inform the CPU that the timer operation has been completed. When the timer counter reaches zero, the value of corresponding TCNTBn is automatically loaded into the down counter to continue the next operation. However, if the timer stops, for example, by clearing the timer enable bit of TCONn during the timer running mode, the value of TCNTBn will not be reloaded into the counter. The value of TCMPBn is used for pulse width modulation (PWM). The timer control logic changes the output level when the down-counter value matches the value of the compare register in the timer control logic. Therefore, the compare register determines the turn-on time (or turn-off time) of a PWM output.
FEATURE -- Five 16-bit timers -- Two 8-bit prescalers & Two 4-bit divider -- Programmable duty control of output waveform (PWM) -- Auto reload mode or one-shot pulse mode -- Dead-zone generator
10-1
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
PWM TIMER
S3C2440X RISC MICROPROCESSOR
TCMPB0
TCNTB0 Dead Zone Generator Control Logic0
TOUT0
5:1 MUX
Dead Zone
PCLK 8-Bit Prescaler
1/2 1/4 1/8 1/16 TCLK0 Clock Divider
TCMPB1
TCNTB1 TOUT1
5:1 MUX TCMPB2 5:1 MUX
Control Logic1
Dead Zone
TCNTB2
Control Logic2
TOUT2
1/2 8-Bit Prescaler 1/4 1/8 1/16 TCLK1 Clock Divider
TCMPB3
TCNTB3
Control Logic3
TOUT3
Figure 10-1. 16-bit PWM Timer Block Diagram
5:1 MUX 5:1 MUX
TCNTB4
Control Logic4
No Pin
10-2
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
PWM TIMER
PWM TIMER OPERATION
PRESCALER & DIVIDER An 8-bit prescaler and a 4-bit divider make the following output frequencies: 4-bit divider settings 1/2 (PCLK = 50 MHz) 1/4 (PCLK = 50 MHz) 1/8 (PCLK = 50 MHz) 1/16 (PCLK = 50 MHz) BASIC TIMER OPERATION Minimum resolution (prescaler = 0) 0.0400 us (25.0000 MHz) 0.0800 us (12.5000 MHz) 0.1600 us ( 6.2500 MHz) 0.3200 us ( 3.1250 MHz) Maximum resolution (prescaler = 255) 10.2400 us (97.6562 KHz) 20.4800 us (48.8281 KHz) 40.9601 us (24.4140 KHz) 81.9188 us (12.2070 KHz) Maximum interval (TCNTBn = 65535) 0.6710 sec 1.3421 sec 2.6843 sec 5.3686 sec
Start bit=1
Timer is started TCNTn=TCMPn Auto-reload
TCNTn=TCMPn
Timer is stopped
TCMPn
1
0
TCNTn
3
3
2
1
0
2
1
0
0
TCNTBn=3 TCNTBn=1 Manual update=1 Auto-reload=1
TCNTBn=2 TCNTBn=0 Manual update=0 Auto-reload=1
Auto-reload Interrupt request Interrupt request
TOUTn
Command Status
Figure 10-2. Timer Operations
A timer (except the timer ch-5) has TCNTBn, TCNTn, TCMPBn and TCMPn. (TCNTn and TCMPn are the names of the internal registers. The TCNTn register can be read from the TCNTOn register) The TCNTBn and the TCMPBn are loaded into the TCNTn and the TCMPn when the timer reaches 0. When the TCNTn reaches 0, an interrupt request will occur if the interrupt is enabled.
10-3
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
PWM TIMER
S3C2440X RISC MICROPROCESSOR
AUTO RELOAD & DOUBLE BUFFERING S3C2440X PWM Timers have a double buffering function, enabling the reload value changed for the next timer operation without stopping the current timer operation. So, although the new timer value is set, a current timer operation is completed successfully. The timer value can be written into Timer Count Buffer register (TCNTBn) and the current counter value of the timer can be read from Timer Count Observation register (TCNTOn). If the TCNTBn is read, the read value does not indicate the current state of the counter but the reload value for the next timer duration. The auto-reload operation copies the TCNTBn into TCNTn when the TCNTn reaches 0. The value, written into the TCNTBn, is loaded to the TCNTn only when the TCNTn reaches 0 and auto reload is enabled. If the TCNTn becomes 0 and the auto reload bit is 0, the TCNTn does not operate any further.
Write TCNTBn = 100 Start TCNTBn = 150
Write TCNTBn = 200
Auto-reload 150 Interrupt 100 100 200
Figure 10-3. Example of Double Buffering Function
10-4
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
PWM TIMER
TIMER INITIALIZATION USING MANUAL UPDATE BIT AND INVERTER BIT An auto reload operation of the timer occurs when the down counter reaches 0. So, a starting value of the TCNTn has to be defined by the user in advance. In this case, the starting value has to be loaded by the manual update bit. The following steps describe how to start a timer: 1) Write the initial value into TCNTBn and TCMPBn. 2) Set the manual update bit of the corresponding timer. It is recommended that you configure the inverter on/off bit. (whether use inverter or not). 3) Set start bit of the corresponding timer to start the timer (and clear the manual update bit). If the timer is stopped by force, the TCNTn retains the counter value and is not reloaded from TCNTBn. If a new value has to be set, perform manual update. NOTE Whenever TOUT inverter on/off bit is changed, the TOUTn logic value will also be changed whether the timer runs. Therefore, it is desirable that the inverter on/off bit is configured with the manual update bit.
10-5
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
PWM TIMER
S3C2440X RISC MICROPROCESSOR
TIMER OPERATION
1
2
3
4
6
79
10
TOUTn 50 110 40 40 20 60
5
8
11
Figure 10-4. Example of a Timer Operation Figure 10-4 shows the result of the following procedure: 1. Enable the auto reload function. Set the TCNTBn to 160 (50+110) and the TCMPBn to 110. Set the manual update bit and configure the inverter bit (on/off). The manual update bit sets TCNTn and TCMPn to the values of TCNTBn and TCMPBn, respectively. And then, set the TCNTBn and the TCMPBn to 80 (40+40) and 40, respectively, to determine the next reload value. 2. Set the start bit, provided that manual_update is 0 and the inverter is off and auto reload is on. The timer starts counting down after latency time within the timer resolution. 3. When the TCNTn has the same value as that of the TCMPn, the logic level of the TOUTn is changed from low to high. 4. When the TCNTn reaches 0, the interrupt request is generated and TCNTBn value is loaded into a temporary register. At the next timer tick, the TCNTn is reloaded with the temporary register value (TCNTBn). 5. In Interrupt Service Routine (ISR), the TCNTBn and the TCMPBn are set to 80 (20+60) and 60, respectively, for the next duration. 6. When the TCNTn has the same value as the TCMPn, the logic level of TOUTn is changed from low to high. 7. When the TCNTn reaches 0, the TCNTn is reloaded automatically with the TCNTBn, triggering an interrupt request. 8. In Interrupt Service Routine (ISR), auto reload and interrupt request are disabled to stop the timer. 9. When the value of the TCNTn is same as the TCMPn, the logic level of the TOUTn is changed from low to high. 10. Even when the TCNTn reaches 0, the TCNTn is not any more reloaded and the timer is stopped because auto reload has been disabled. 11. No more interrupt requests are generated.
10-6
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
PWM TIMER
PULSE WIDTH MODULATION (PWM)
60
50
40
30
30
Write TCMPBn = 60 Write TCMPBn = 50
Write TCMPBn = 40 Write TCMPBn = 30
Write TCMPBn = 30 Write TCMPBn = Next PWM Value
Figure 10-5. Example of PWM PWM function can be implemented by using the TCMPBn. PWM frequency is determined by TCNTBn. Figure 10-5 shows a PWM value determined by TCMPBn. For a higher PWM value, decrease the TCMPBn value. For a lower PWM value, increase the TCMPBn value. If an output inverter is enabled, the increment/decrement may be reversed. The double buffering function allows the TCMPBn, for the next PWM cycle, written at any point in the current PWM cycle by ISR or other routine.
10-7
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
PWM TIMER
S3C2440X RISC MICROPROCESSOR
OUTPUT LEVEL CONTROL
Inverter off
Inverter on Initial State Period 1 Period 2 Timer Stop
Figure 10-6. Inverter On/Off The following procedure describes how to maintain TOUT as high or low (assume the inverter is off): 1. Turn off the auto reload bit. And then, TOUTn goes to high level and the timer is stopped after the TCNTn reaches 0 (recommended). 2. Stop the timer by clearing the timer start/stop bit to 0. If TCNTn TCMPn, the output level is high. If TCNTn >TCMPn, the output level is low. 3. The TOUTn can be inverted by the inverter on/off bit in TCON. The inverter removes the additional circuit to adjust the output level.
10-8
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
PWM TIMER
DEAD ZONE GENERATOR The dead zone is for the PWM control in a power device. This function enables the insertion of the time gap between a turn-off of a switching device and a turn on of another switching device. This time gap prohibits the two switching devices from being turned on simultaneously, even for a very short time. TOUT0 is the PWM output. nTOUT0 is the inversion of the TOUT0. If the dead zone is enabled, the output wave form of TOUT0 and nTOUT0 will be TOUT0_DZ and nTOUT0_DZ, respectively. nTOUT0_DZ is routed to the TOUT1 pin. In the dead zone interval, TOUT0_DZ and nTOUT0_DZ can never be turned on simultaneously.
TOUT0
nTOUT0
Deadzone Interval
TOUT0_DZ
nTOUT0_DZ
Figure 10-7. The Wave Form When a Dead Zone Feature is Enabled
10-9
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
PWM TIMER
S3C2440X RISC MICROPROCESSOR
DMA REQUEST MODE The PWM timer can generate a DMA request at every specific time. The timer keeps DMA request signals (nDMA_REQ) low until the timer receives an ACK signal. When the timer receives the ACK signal, it makes the request signal inactive. The timer, which generates the DMA request, is determined by setting DMA mode bits (in TCFG1 register). If one of timers is configured as DMA request mode, that timer does not generate an interrupt request. The others can generate interrupt normally. DMA mode configuration and DMA / interrupt operation
DMA Mode 0000 0001 0010 0011 0100 0101 0110 DMA Request No select Timer0 Timer1 Timer2 Timer3 Timer4 No select Timer0 INT ON OFF ON ON ON ON ON Timer1 INT ON ON OFF ON ON ON ON Timer2 INT ON ON ON OFF ON ON ON Timer3 INT ON ON ON ON OFF ON ON Timer4 INT ON ON ON ON ON OFF ON
PCLK
INT4tmp
DMAreq_en
101
nDMA_ACK
nDMA_REQ
INT4
Figure 10-8. Timer4 DMA Mode Operation
10-10
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
PWM TIMER
PWM TIMER CONTROL REGISTERS
TIMER CONFIGURATION REGISTER0 (TCFG0) Timer input clock Frequency = PCLK / {prescaler value+1} / {divider value} {prescaler value} = 0~255 {divider value} = 2, 4, 8, 16 Register TCFG0 Address 0x51000000 R/W R/W Description Configures the two 8-bit prescalers Reset Value 0x00000000
TCFG0 Reserved Dead zone length Prescaler 1 Prescaler 0
Bit [31:24] [23:16] [15:8] [7:0]
Description These 8 bits determine the dead zone length. The 1 unit time of the dead zone length is equal to that of timer 0. These 8 bits determine prescaler value for Timer 2, 3 and 4. These 8 bits determine prescaler value for Timer 0 and 1.
Initial State 0x00 0x00 0x00 0x00
10-11
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
PWM TIMER
S3C2440X RISC MICROPROCESSOR
TIMER CONFIGURATION REGISTER1 (TCFG1) Register TCFG1 Address 0x51000004 R/W R/W Description 5-MUX & DMA mode selecton register Reset Value 0x00000000
TCFG1 Reserved DMA mode
Bit [31:24] [23:20]
Description Select DMA request channel 0000 = No select (all interrupt) 0001 = Timer0 0010 = Timer1 0011 = Timer2 0100 = Timer3 0101 = Timer4 0110 = Reserved Select MUX input for PWM Timer4. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = External TCLK1 Select MUX input for PWM Timer3. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = External TCLK1 Select MUX input for PWM Timer2. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = External TCLK1 Select MUX input for PWM Timer1. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = External TCLK0 Select MUX input for PWM Timer0. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = External TCLK0
Initial State 00000000 0000
MUX 4
[19:16]
0000
MUX 3
[15:12]
0000
MUX 2
[11:8]
0000
MUX 1
[7:4]
0000
MUX 0
[3:0]
0000
10-12
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
PWM TIMER
TIMER CONTROL (TCON) REGISTER Register TCON Address 0x51000008 R/W R/W Description Timer control register Reset Value 0x00000000
TCON Timer 4 auto reload on/off Timer 4 manual update (note) Timer 4 start/stop Timer 3 auto reload on/off Timer 3 output inverter on/off Timer 3 manual update (note) Timer 3 start/stop Timer 2 auto reload on/off Timer 2 output inverter on/off Timer 2 manual update (note) Timer 2 start/stop Timer 1 auto reload on/off Timer 1 output inverter on/off Timer 1 manual update (note) Timer 1 start/stop
Note:
Bit [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8]
Description Determine auto reload on/off for Timer 4. 0 = One-shot 1 = Interval mode (auto reload) Determine the manual update for Timer 4. 0 = No operation 1 = Update TCNTB4 Determine start/stop for Timer 4. 0 = Stop 1 = Start for Timer 4 Determine auto reload on/off for Timer 3. 0 = One-shot 1 = Interval mode (auto reload) Determine output inverter on/off for Timer 3. 0 = Inverter off 1 = Inverter on for TOUT3 Determine manual update for Timer 3. 0 = No operation 1 = Update TCNTB3 & TCMPB3 Determine start/stop for Timer 3. 0 = Stop 1 = Start for Timer 3 Determine auto reload on/off for Timer 2. 0 = One-shot 1 = Interval mode (auto reload) Determine output inverter on/off for Timer 2. 0 = Inverter off 1 = Inverter on for TOUT2 Determine the manual update for Timer 2. 0 = No operation 1 = Update TCNTB2 & TCMPB2 Determine start/stop for Timer 2. 0 = Stop 1 = Start for Timer 2 Determine the auto reload on/off for Timer1. 0 = One-shot 1 = Interval mode (auto reload) Determine the output inverter on/off for Timer1. 0 = Inverter off 1 = Inverter on for TOUT1 Determine the manual update for Timer 1. 0 = No operation 1 = Update TCNTB1 & TCMPB1 Determine start/stop for Timer 1. 0 = Stop 1 = Start for Timer 1
Initial state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The bits have to be cleared at next writing.
10-13
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
PWM TIMER
S3C2440X RISC MICROPROCESSOR
TCON (Continued) TCON Reserved Dead zone enable Timer 0 auto reload on/off Timer 0 output inverter on/off Timer 0 manual update (note) Timer 0 start/stop Bit [7:5] Reserved [4] [3] [2] [1] [0] Determine the dead zone operation. 0 = Disable 1 = Enable Determine auto reload on/off for Timer 0. 0 = One-shot 1 = Interval mode(auto reload) Determine the output inverter on/off for Timer 0. 0 = Inverter off 1 = Inverter on for TOUT0 Determine the manual update for Timer 0. 0 = No operation 1 = Update TCNTB0 & TCMPB0 Determine start/stop for Timer 0. 0 = Stop 1 = Start for Timer 0 0 0 0 0 0 Description Initial state
NOTE: The bit have to be cleared at next writing.
10-14
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
PWM TIMER
TIMER 0 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB0/TCMPB0) Register TCNTB0 TCMPB0 Address 0x5100000C 0x51000010 R/W R/W R/W Description Timer 0 count buffer register Timer 0 compare buffer register Reset Value 0x00000000 0x00000000
TCMPB0 Timer 0 compare buffer register
Bit [15:0]
Description Set compare buffer value for Timer 0
Initial State 0x00000000
TCNTB0 Timer 0 count buffer register
Bit [15:0]
Description Set count buffer value for Timer 0
Initial State 0x00000000
TIMER 0 COUNT OBSERVATION REGISTER (TCNTO0) Register TCNTO0 Address 0x51000014 R/W R Description Timer 0 count observation register Reset Value 0x00000000
TCNTO0 Timer 0 observation register
Bit [15:0]
Description Set count observation value for Timer 0
Initial State 0x00000000
10-15
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
PWM TIMER
S3C2440X RISC MICROPROCESSOR
TIMER 1 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB1/TCMPB1) Register TCNTB1 TCMPB1 Address 0x51000018 0x5100001C R/W R/W R/W Description Timer 1 count buffer register Timer 1 campare buffer register Reset Value 0x00000000 0x00000000
TCMPB1 Timer 1 compare buffer register
Bit [15:0]
Description Set compare buffer value for Timer 1
Initial State 0x00000000
TCNTB1 Timer 1 count buffer register
Bit [15:0]
Description Set count buffer value for Timer 1
Initial State 0x00000000
TIMER 1 COUNT OBSERVATION REGISTER (TCNTO1) Register TCNTO1 Address 0x51000020 R/W R Description Timer 1 count observation register Reset Value 0x00000000
TCNTO1 Timer 1 observation register
Bit [15:0]
Description Set count observation value for Timer 1
initial state 0x00000000
10-16
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
PWM TIMER
TIMER 2 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB2/TCMPB2) Register TCNTB2 TCMPB2 Address 0x51000024 0x51000028 R/W R/W R/W Description Timer 2 count buffer register Timer 2 campare buffer register Reset Value 0x00000000 0x00000000
TCMPB2 Timer 2 compare buffer register
Bit [15:0]
Description Set compare buffer value for Timer 2
Initial State 0x00000000
TCNTB2 Timer 2 count buffer register
Bit [15:0]
Description Set count buffer value for Timer 2
Initial State 0x00000000
TIMER 2 COUNT OBSERVATION REGISTER (TCNTO2) Register TCNTO2 Address 0x5100002C R/W R Description Timer 2 count observation register Reset Value 0x00000000
TCNTO2 Timer 2 observation register
Bit [15:0]
Description Set count observation value for Timer 2
Initial State 0x00000000
10-17
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
PWM TIMER
S3C2440X RISC MICROPROCESSOR
TIMER 3 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB3/TCMPB3) Register TCNTB3 TCMPB3 Address 0x51000030 0x51000034 R/W R/W R/W Description Timer 3 count buffer register Timer 3 campare buffer register Reset Value 0x00000000 0x00000000
TCMPB3 Timer 3 compare buffer register
Bit [15:0]
Description Set compare buffer value for Timer 3
Initial State 0x00000000
TCNTB3 Timer 3 count buffer register
Bit [15:0]
Description Set count buffer value for Timer 3
Initial State 0x00000000
TIMER 3 COUNT OBSERVATION REGISTER (TCNTO3) Register TCNTO3 Address 0x51000038 R/W R Description Timer 3 count observation register Reset Value 0x00000000
TCNTO3 Timer 3 observation register
Bit [15:0]
Description Set count observation value for Timer 3
Initial State 0x00000000
10-18
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
PWM TIMER
TIMER 4 COUNT BUFFER REGISTER (TCNTB4) Register TCNTB4 Address 0x5100003C R/W R/W Description Timer 4 count buffer register Reset Value 0x00000000
TCNTB4 Timer 4 count buffer register
Bit [15:0]
Description Set count buffer value for Timer 4
Initial State 0x00000000
TIMER 4 COUNT OBSERVATION REGISTER (TCNTO4) Register TCNTO4 Address 0x51000040 R/W R Description Timer 4 count observation register Reset Value 0x00000000
TCNTO4 Timer 4 observation register
Bit [15:0]
Description Set count observation value for Timer 4
Initial State 0x00000000
10-19
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
PWM TIMER
S3C2440X RISC MICROPROCESSOR
NOTES
10-20
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
UART
11
OVERVIEW
UART
The S3C2440X Universal Asynchronous Receiver and Transmitter (UART) provide three independent asynchronous serial I/O (SIO) ports, each of which can operate in Interrupt-based or DMA-based mode. In other words,the UART can generate an interrupt or a DMA request to transfer data between CPU and the UART. The UART can support bit rates of up to 115.2K bps using system clock. If an external device provides the UART with UARTCLK, then the UART can operate at higher speed. Each UART channel contains two 64-byte FIFOs for receiver and transmitter. The S3C2440X UART includes programmable baud rates, infrared (IR) transmit/receive, one or two stop bit insertion, 5-bit, 6-bit, 7-bit or 8-bit data width and parity checking. Each UART contains a baud-rate generator,a transmitter,a receiver and a control unit, as shown in Figure 11-1. The baud-rate generator can be clocked by PCLK or UARTCLK. The transmitter and the receiver contain 64-byte FIFOs and data shifters. Data is written to FIFO and then copied to the transmit shifter before being transmitted. The data is then shifted out by the transmit data pin (TxDn). Meanwhile, received data is shifted from the receive data pin (RxDn), and then copied to FIFO from the shifter.
FEATURES
-- RxD0, TxD0, RxD1, TxD1, RxD2,and TxD2 with DMA-based or interrupt-based operation -- UART Ch 0, 1,and 2 with IrDA 1.0 & 64-byte FIFO -- UART Ch 0 and 1 with nRTS0, nCTS0, nRTS1,and nCTS1 -- Supports handshake transmit/receive
11-1
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
UART
S3C2440X RISC MICROPROCESSOR
BLOCK DIAGRAM
Peripheral BUS
Transmitter
Transmit FIFO Register (FIFO mode) Transmit Buffer Register(64 Byte)
Transmit Holding Register (Non-FIFO mode)
Transmit Shifter
TXDn
Control Unit Receiver
Buad-rate Generator
Clock Source
Receive Shifter
RXDn
Receive Buffer Register(64 Byte)
Receive Holding Register (Non-FIFO mode only)
Receive FIFO Register (FIFO mode)
In FIFO mode, all 64 Byte of Buffer register are used as FIFO register. In non-FIFO mode, only 1 Byte of Buffer register is used as Holding register.
Figure 11-1 UART Block Diagram (with FIFO)
11-2
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
UART
UART OPERATION The following sections describe the UART operations that include data transmission, data reception, interrupt generation, baud-rate generation, Loopback mode, Infrared mode, and auto flow control. Data Transmission The data frame for transmission is programmable. It consists of a start bit, 5 to 8 data bits, an optional parity bit and 1 to 2 stop bits, which can be specified by the line control register (ULCONn). The transmitter can also produce the break condition, which forces the serial output to logic 0 state for one frame transmission time. This block transmits break signals after the present transmission word is transmitted completely. After the break signal transmission, it continuously transmits data into the Tx FIFO (Tx holding register in the case of Non-FIFO mode). Data Reception Like the transmission, the data frame for reception is also programmable. It consists of a start bit, 5 to 8 data bits, an optional parity bit and 1 to 2 stop bits in the line control register (ULCONn). The receiver can detect overrun error. The overrun error indicates that new data has overwritten the old data before the old data has been read. Receive time-out condition occurs when it does not receive any data during the 3 word time (this interval follows the setting of Word Length bit) and the Rx FIFO is not empty in the FIFO mode. Auto Flow Control (AFC) The S3C2440X's UART 0 and UART 1 support auto flow control with nRTS and nCTS signals. In case, it can be connected to external UARTs. If users want to connect a UART to a Modem, disable auto flow control bit in UMCONn register and control the signal of nRTS by software. In AFC, nRTS depends on the condition of the receiver and nCTS signals control the operation of the transmitter. The UART's transmitter transfers the data in FIFO only when nCTS signals are activated (in AFC, nCTS means that other UART's FIFO is ready to receive data). Before the UART receives data, nRTS has to be activated when its receive FIFO has a spare more than 32-byte and has to be inactivated when its receive FIFO has a spare under 32-byte (in AFC, nRTS means that its own receive FIFO is ready to receive data).
Transmission case in UART A UART A TxD nCTS UART B RxD nRTS Reception case in UART A UART A RxD nRTS UART B TxD nCTS
Figure 11-2 UART AFC interface Note: UART 2 does not support AFC function, because the S3C2440X has no nRTS2 and nCTS2.
11-3
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
UART
S3C2440X RISC MICROPROCESSOR
Example of Non Auto-Flow control (controlling nRTS and nCTS by software) Rx operation with FIFO 1. Select receive mode (Interrupt or DMA mode). 2. Check the value of Rx FIFO count in UFSTATn register. If the value is less than 32, users have to set the value of UMCONn[0] to '1' (activating nRTS), and if it is equal or larger than 32 users have to set the value to '0' (inactivating nRTS). 3. Repeat the Step 2. Tx operation with FIFO 1. Select transmit mode (Interrupt or DMA mode). 2. Check the value of UMSTATn[0]. If the value is '1' (activating nCTS), users write the data to Tx FIFO register.
11-4
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
UART
RS-232C interface If users want to connect the UART to modem interface (instead of null modem), nRTS, nCTS, nDSR, nDTR, DCD and nRI signals are needed. In this case, the users can control these signals with general I/O ports by software because the AFC does not support the RS-232C interface. Interrupt/DMA Request Generation Each UART of the S3C2440X has seven status (Tx/Rx/Error) signals: Overrun error, Receive buffer data ready, Transmit buffer empty, and Transmit shifter empty, all of which are indicated by the corresponding UART status register (UTRSTATn/UERSTATn). The overrun error can cause the receive error status interrupt request, if the receive-error-status-interrupt-enable bit is set to one in the control register, UCONn. When a receive-error-status-interrupt-request is detected, the signal causing the request can be identified by reading the value of UERSTSTn. When the receiver transfers the data of the receive shifter to the receive FIFO register in FIFO mode and the number of received data reaches Rx FIFO Trigger Level, Rx interrupt is generated, if Receive mode in control register (UCONn) is selected as 1 (Interrupt request or polling mode). In the Non-FIFO mode, transferring the data of the receive shifter to the receive holding register will cause Rx interrupt under the Interrupt request and polling mode. When the transmitter transfers data from its transmit FIFO register to its transmit shifter and the number of data left in transmit FIFO reaches Tx FIFO Trigger Level, Tx interrupt is generated, if Transmit mode in control register is selected as Interrupt request or polling mode. In the Non-FIFO mode, transferring data from the transmit holding register to the transmit shifter will cause Tx interrupt under the Interrupt request and polling mode. If the Receive mode and Transmit mode in control register are selected as the DMAn request mode then DMAn request occurs instead of Rx or Tx interrupt in the situation mentioned above. Table 11-1 Interrupts in Connection with FIFO Type Rx interrupt FIFO Mode Generated whenever receive data reaches the trigger level of receive FIFO. Generated when the number of data in FIFO does not reaches Rx FIFO trigger Level and does not receive any data during 3 word time (receive time out). This interval follows the setting of Word Length bit. Tx interrupt Generated whenever transmit data reaches the trigger level of transmit FIFO (Tx FIFO trigger Level). Overrun error will be generated, when it gets to the top of the receive FIFO without reading out data in it. Generated by the transmit holding register whenever transmit buffer becomes empty. Overrun error generates an error interrupt immediately. Non-FIFO Mode Generated by the receive holding register whenever receive buffer becomes full.
Error interrupt
11-5
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
UART
S3C2440X RISC MICROPROCESSOR
Baud-Rate Generation Each UART's baud-rate generator provides the serial clock for the transmitter and the receiver. The source clock for the baud-rate generator can be selected with the S3C2440X's internal system clock or UARTCLK. In other words, dividend is selectable by setting Clock Selection of UCONn. The baud-rate clock is generated by dividing the source clock (PCLK or UARTCLK) by 16 and a 16-bit divisor specified in the UART baud-rate divisor register (UBRDIVn). The UBRDIVn can be determined by the following expression: UBRDIVn = (int)(PCLK/(bps x 16) ) -1
Where, UBRDIVn should be from 1 to (216-1). For accurate UART operation, the S3C2440X also supports UARTCLK as a dividend. If the S3C2440X uses UARTCLK, which is supplied by an external UART device or system, then the serial clock of UART is exactly synchronized with UARTCLK. So, the user can get the more precise UART operation. The UBRDIVn can be determined: UBRDIVn = (int)(UARTCLK / (bps x 16) ) -1
16
Where, UBRDIVn should be from 1 to (2 -1) and UARTCLK should be smaller than PCLK. For example, if the baud-rate is 115200 bps and PCLK or UARTCLK is 40 MHz, UBRDIVn is determined: UBRDIVn = (int)(40000000/(115200 x 16)) -1 = (int)(21.7) -1 = 21 -1 = 20
Loopback Mode The S3C2440X UART provides a test mode referred to as the Loopback mode, to aid in isolating faults in the communication link.This mode structurally enables the connection of RXD and TXD in the UART. In this mode, therefore, transmitted data is received to the receiver, via RXD. This feature allows the processor to verify the internal transmit and to receive the data path of each SIO channel. This mode can be selected by setting the loopback bit in the UART control register (UCONn).
Break Condition The break is defined as a continuous low level signal for one frame transmission time on the transmit data output.
11-6
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
UART
Infrared (IR) Mode The S3C2440X UART block supports infrared (IR) transmission and reception, which can be selected by setting the Infrared-mode bit in the UART line control register (ULCONn). Figure 11-4 illustrates how to implement the IR mode. In IR transmit mode, the transmit pulse comes out at a rate of 3/16, the normal serial transmit rate (when the transmit data bit is zero); In IR receive mode, the receiver must detect the 3/16 pulsed period to recognize a zero value (see the frame timing diagrams shown in Figure 11-6 and 11-7).
TxD
0 TxD 1
IRS UART Block RxD 1 RE IrDA Tx Encoder IrDA Rx Decoder 0 RxD
Figure 11-3. IrDA Function Block Diagram
11-7
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
UART
S3C2440X RISC MICROPROCESSOR
SIO Frame Start Bit Data Bits Stop Bit
0
1
0
1
0
0
1
1
0
1
Figure 11-4. Serial I/O Frame Timing Diagram (Normal UART)
IR Transmit Frame Start Bit Data Bits Stop Bit
0
1
0
1
0
0
1
1
0
1
Bit Time
Pulse Width = 3/16 Bit Frame
Figure 11-5. Infrared Transmit Mode Frame Timing Diagram
IR Receive Frame Start Bit Data Bits Stop Bit
0
1
0
1
0
0
1
1
0
1
Figure 11-6. Infrared Receive Mode Frame Timing Diagram
11-8
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
UART
UART SPECIAL REGISTERS
UART LINE CONTROL REGISTER There are three UART line control registers including ULCON0, ULCON1, and ULCON2 in the UART block. Register ULCON0 ULCON1 ULCON2 Address 0x50000000 0x50004000 0x50008000 R/W R/W R/W R/W Description UART channel 0 line control register UART channel 1 line control register UART channel 2 line control register Reset Value 0x00 0x00 0x00
ULCONn Reserved Infrared Mode
Bit [7] [6]
Description Determine whether or not to use the Infrared mode. 0 = Normal mode operation 1 = Infrared Tx/Rx mode
Initial State 0 0
Parity Mode
[5:3]
Specify the type of parity generation and checking during UART transmit and receive operation. 0xx = No parity 100 = Odd parity 101 = Even parity 110 = Parity forced/checked as 1 111 = Parity forced/checked as 0
000
Number of Stop Bit
[2]
Specify how many stop bits are to be used for end-of-frame signal. 0 = One stop bit per frame 1 = Two stop bit per frame
0
Word Length
[1:0]
Indicate the number of data bits to be transmitted or received per frame. 00 = 5-bits 10 = 7-bits 01 = 6-bits 11 = 8-bits
00
11-9
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
UART
S3C2440X RISC MICROPROCESSOR
UART CONTROL REGISTER There are three UART control registers including UCON0, UCON1 and UCON2 in the UART block. Register UCON0 UCON1 UCON2 Address 0x50000004 0x50004004 0x50008004 R/W R/W R/W R/W Description UART channel 0 control register UART channel 1 control register UART channel 2 control register Reset Value 0x00 0x00 0x00
UCONn Clock Selection
Bit
Description 0=PCLK : UBRDIVn = (int)(PCLK / (bps x 16) ) -1 1=UARTCLK : UBRDIVn = (int)(UARTCLK / (bps x 16) ) -1
Initial State 0
[10] Select PCLK or UARTCLK for the UART baud rate.
Tx Interrupt Type
[9]
Interrupt request type. 0 = Pulse (Interrupt is requested as soon as the Tx buffer becomes empty in Non-FIFO mode or reaches Tx FIFO Trigger Level in FIFO mode.) 1 = Level (Interrupt is requested while Tx buffer is empty in Non-FIFO mode or reaches Tx FIFO Trigger Level in FIFO mode.)
0
Rx Interrupt Type
[8]
Interrupt request type. 0 = Pulse (Interrupt is requested the instant Rx buffer receives the data in Non-FIFO mode or reaches Rx FIFO Trigger Level in FIFO mode.) 1 = Level (Interrupt is requested while Rx buffer is receiving data in Non-FIFO mode or reaches Rx FIFO Trigger Level in FIFO mode.)
0
Rx Time Out Enable Rx Error Status Interrupt Enable
[7]
Enable/Disable Rx time out interrupt when UART FIFO is enabled. The interrupt is a receive interrupt. 0 = Disable 1 = Enable This bit enables the UART to generate an interrupt if overrun error occurs during a receive operation 0 = Do not generate receive error status interrupt. 1 = Generate receive error status interrupt.
0
[6]
0
Loopback Mode
[5]
Setting loopback bit to 1 causes the UART to enter the loopback mode. This mode is provided for test purposes only. 0 = Normal operation 1 = Loopback mode Setting this bit causes the UART to send a break during 1 frame time. This bit is automatically cleared after sending the break signal. 0 = Normal transmit 1 = Send break signal
0
Send Break Signal
[4]
0
11-10
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
UART
UART CONTROL REGISTER (CONTINUED) Transmit Mode [3:2] Determine which function is currently able to write Tx data to the UART transmit buffer register. (UART Tx Enable/Disable) 00 = Disable 01 = Interrupt request or polling mode 10 = DMA0 request (Only for UART0), DMA3 request (Only for UART2) 11 = DMA1 request (Only for UART1) Receive Mode [1:0] Determine which function is currently able to read data from UART receive buffer register. (UART Rx Enable/Disable) 00 = Disable 01 = Interrupt request or polling mode 10 = DMA0 request (Only for UART0), DMA3 request (Only for UART2) 11 = DMA1 request (Only for UART1)
Note: When the UART does not reach the FIFO trigger level and does not receive data during 3 word time in DMA receive mode with FIFO, the Rx interrupt will be generated (receive time out), and the users should check the FIFO status and read out the rest.
00
00
11-11
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
UART
S3C2440X RISC MICROPROCESSOR
UART FIFO CONTROL REGISTER There are three UART FIFO control registers including UFCON0, UFCON1 and UFCON2 in the UART block. Register UFCON0 UFCON1 UFCON2 Address 0x50000008 0x50004008 0x50008008 R/W R/W R/W R/W Description UART channel 0 FIFO control register UART channel 1 FIFO control register UART channel 2 FIFO control register Reset Value 0x0 0x0 0x0
UFCONn Tx FIFO Trigger Level
Bit [7:6]
Description Determine the trigger level of transmit FIFO. 00 = Empty 01 = 16-byte 10 = 32-byte 11 = 48-byte Determine the trigger level of receive FIFO. 00 = 1-byte 01 = 8-byte 10 = 16-byte 11 = 32-byte Auto-cleared after resetting FIFO 0 = Normal 1= Tx FIFO reset Auto-cleared after resetting FIFO 0 = Normal 1= Rx FIFO reset 0 = Disable 1 = Enable
Initial State 00
Rx FIFO Trigger Level
[5:4]
00
Reserved Tx FIFO Reset Rx FIFO Reset FIFO Enable
[3] [2] [1] [0]
0 0 0 0
Note: When the UART does not reach the FIFO trigger level and does not receive data during 3 word time in DMA receive mode with FIFO, the Rx interrupt will be generated (receive time out), and the users should check the FIFO status and read out the rest.
11-12
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
UART
UART MODEM CONTROL REGISTER There are two UART MODEM control registers including UMCON0 and UMCON1 in the UART block. Register UMCON0 UMCON1 Reserved Address 0x5000000C 0x5000400C 0x5000800C R/W R/W R/W Description UART channel 0 Modem control register UART channel 1 Modem control register Reserved Reset Value 0x0 0x0 Undef
UMCONn Reserved Auto Flow Control (AFC) Reserved Request to Send
Bit [7:5] [4] [3:1] [0] These bits must be 0's 0 = Disable These bits must be 0's
Description 1 = Enable
Initial State 00 0 00 0
If AFC bit is enabled, this value will be ignored. In this case the S3C2440X will control nRTS automatically. If AFC bit is disabled, nRTS must be controlled by software. 0 = 'H' level (Inactivate nRTS) 1 = 'L' level (Activate nRTS)
Note: UART 2 does not support AFC function, because the S3C2440X has no nRTS2 and nCTS2.
11-13
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
UART
S3C2440X RISC MICROPROCESSOR
UART TX/RX STATUS REGISTER There are three UART Tx/Rx status registers including UTRSTAT0, UTRSTAT1 and UTRSTAT2 in the UART block. Register UTRSTAT0 UTRSTAT1 UTRSTAT2 Address 0x50000010 0x50004010 0x50008010 R/W R R R Description UART channel 0 Tx/Rx status register UART channel 1 Tx/Rx status register UART channel 2 Tx/Rx status register Reset Value 0x6 0x6 0x6
UTRSTATn Transmitter empty
Bit [2]
Description Set to 1 automatically when the transmit buffer register has no valid data to transmit and the transmit shift register is empty. 0 = Not empty 1 = Transmitter (transmit buffer & shifter register) empty Set to 1 automatically when transmit buffer register is empty. 0 =The buffer register is not empty 1 = Empty (In Non-FIFO mode, Interrupt or DMA is requested. In FIFO mode, Interrupt or DMA is requested, when Tx FIFO Trigger Level is set to 00 (Empty)) If the UART uses the FIFO, users should check Tx FIFO Count bits and Tx FIFO Full bit in the UFSTAT register instead of this bit.
Initial State 1
Transmit buffer empty
[1]
1
Receive buffer data ready
[0]
Set to 1 automatically whenever receive buffer register contains valid data, received over the RXDn port. 0 = Empty 1 = The buffer register has a received data (In Non-FIFO mode, Interrupt or DMA is requested) If the UART uses the FIFO, users should check Rx FIFO Count bits and Rx FIFO Full bit in the UFSTAT register instead of this bit.
0
11-14
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
UART
UART ERROR STATUS REGISTER There are three UART Rx error status registers including UERSTAT0, UERSTAT1 and UERSTAT2 in the UART block. Register UERSTAT0 UERSTAT1 UERSTAT2 Address 0x50000014 0x50004014 0x50008014 R/W R R R Description UART channel 0 Rx error status register UART channel 1 Rx error status register UART channel 2 Rx error status register Reset Value 0x0 0x0 0x0
UERSTATn Overrun Error
Bit [0]
Description Set to 1 automatically whenever an overrun error occurs during receive operation. 0 = No overrun error during receive 1 = Overrun error (Interrupt is requested.)
Initial State 0
Note: This bit is automatically cleared to 0 when the UART error status register is read.
11-15
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
UART
S3C2440X RISC MICROPROCESSOR
UART FIFO STATUS REGISTER There are three UART FIFO status registers including UFSTAT0, UFSTAT1 and UFSTAT2 in the UART block. Register UFSTAT0 UFSTAT1 UFSTAT2 Address 0x50000018 0x50004018 0x50008018 R/W R R R Description UART channel 0 FIFO status register UART channel 1 FIFO status register UART channel 2 FIFO status register Reset Value 0x00 0x00 0x00
UFSTATn Reserved Tx FIFO Full
Bit [15] [14]
Description Set to 1 automatically whenever transmit FIFO is full during transmit operation 0 = 0-byte Tx FIFO data 63-byte 1 = Full Number of data in Tx FIFO Set to 1 automatically whenever receive FIFO is full during receive operation 0 = 0-byte Rx FIFO data 63-byte 1 = Full Number of data in Rx FIFO
Initial State 0 0
Tx FIFO Count Reserved Rx FIFO Full
[13:8] [7] [6]
0 0 0
Rx FIFO Count
[5:0]
0
11-16
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
UART
UART MODEM STATUS REGISTER There are two UART modem status registers including UMSTAT0, UMSTAT1 in the UART block. Register UMSTAT0 UMSTAT1 Reserved Address 0x5000001C 0x5000401C 0x5000801C R/W R R Description UART channel 0 Modem status register UART channel 1 Modem status register Reserved Reset Value 0x0 0x0 Undef
UMSTAT0 Reserved Delta CTS
Bit [3] [2]
Description Indicate that the nCTS input to the S3C2440X has changed state since the last time it was read by CPU. (Refer to Figure 11-8.) 0 = Has not changed 1 = Has changed 0 = CTS signal is not activated (nCTS pin is high) 1 = CTS signal is activated (nCTS pin is low)
Initial State 0 0
Reserved Clear to Send
[1] [0]
0 0
nCTS
Delta CTS
Read_UMSTAT
Figure 11-7. nCTS and Delta CTS Timing Diagram
11-17
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
UART
S3C2440X RISC MICROPROCESSOR
UART TRANSMIT BUFFER REGISTER (HOLDING REGISTER & FIFO REGISTER) There are three UART transmit buffer registers including UTXH0, UTXH1 and UTXH2 in the UART block. UTXHn has an 8-bit data for transmission data. Register UTXH0 UTXH1 UTXH2 Address 0x50000020(L) 0x50000023(B) 0x50004020(L) 0x50004023(B) 0x50008020(L) 0x50008023(B) R/W Description Reset Value -
W UART channel 0 transmit buffer register (by byte) W UART channel 1 transmit buffer register (by byte) W UART channel 2 transmit buffer register (by byte)
UTXHn TXDATAn
Bit [7:0]
Description Transmit data for UARTn
Initial State -
Note: (L): The endian mode is Little endian. (B): The endian mode is Big endian.
UART RECEIVE BUFFER REGISTER (HOLDING REGISTER & FIFO REGISTER) There are three UART receive buffer registers including URXH0, URXH1 and URXH2 in the UART block. URXHn has an 8-bit data for received data. Register URXH0 URXH1 URXH2 Address 0x50000024(L) 0x50000027(B) 0x50004024(L) 0x50004027(B) 0x50008024(L) 0x50008027(B) R/W Description Reset Value -
R UART channel 0 receive buffer register (by byte) R UART channel 1 receive buffer register (by byte) R UART channel 2 receive buffer register (by byte)
URXHn RXDATAn
Bit [7:0]
Description Receive data for UARTn
Initial State -
NOTE: When an overrun error occurs, the URXHn must be read. If not, the next received data will also make an overrun error, even though the overrun bit of UERSTATn had been cleared.
11-18
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
UART
UART BAUD RATE DIVISOR REGISTER There are three UART baud rate divisor registers including UBRDIV0, UBRDIV1 and UBRDIV2 in the UART block. The value stored in the baud rate divisor register (UBRDIVn), is used to determine the serial Tx/Rx clock rate (baud rate) as follows: UBRDIVn or UBRDIVn = (int)(UARTCLK / (bps x 16) ) -1
16
= (int)(PCLK / (bps x 16) ) -1
Where, the divisor should be from 1 to (2 -1) and UARTCLK should be smaller than PCLK. For example, if the baud-rate is 115200 bps and PCLK or UARTCLK is 40 MHz, UBRDIVn is: UBRDIVn = (int)(40000000 / (115200 x 16) ) -1 = (int)(21.7) -1 = 21 -1 = 20
Register UBRDIV0 UBRDIV1 UBRDIV2
Address 0x50000028 0x50004028 0x50008028
R/W R/W R/W R/W
Description Baud rate divisior register 0 Baud rate divisior register 1 Baud rate divisior register 2
Reset Value -
UBRDIV n UBRDIV
Bit [15:0]
Description Baud rate division value UBRDIVn >0
Initial State -
11-19
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
USB HOST
USB HOST CONTROLLER
OVERVIEW
S3C2440X supports 2-port USB host interface as follows: * * * * OHCI Rev 1.0 compatible USB Rev1.1 compatible Two down stream ports Support for both LowSpeed and HighSpeed USB devices
OHCI
ROOT HUB
REGS APP_SADR(8) APP_SDATA(32) HCI_DATA(32) CONTROL OHCI REGS CONTROL RCF0_RegData(32) CONTROL USB STATE CONTROL Cntl CONTROL TxEnl ROOT HUB & HOST SIE TxDpls TxDmns PORT S/M PORT S/M 1 X USB V R 2 X USB V R
HCI SLAVE BLOCK
APP_MDATA(32) HCI BUS
HCM_ADR/ DATA(32)
CONTROL
HCI MASTER BLOCK
LIST ED/TD_DATA(32) PROCESSOR BLOCK ED/TD STATUS(32) ED&TD REGS STATUS HC_DATA(8) DF_DATA(8) HCF_DATA(8) 64x8 FIFO Cntl FIFO_DATA(8) Addr(6)
CTRL CTRL
RcvData HSIE S/M RH_DATA(8) DF_DATA(8) DPLL RcvDpls RcvDmns
ROOT HUB & HOST SIE
PORT S/M
EXT.FIFO STATUS
64x8 FIFO
Figure 12-1. USB Host Controller Block Diagram
12-1
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
USB HOST
S3C2440X RISC MICROPROCESSOR
USB HOST CONTROLLER SPECIAL REGISTERS
The S3C2440X USB cost controller complies with OHCI Rev 1.0. Refer to Open Host Controller Interface Rev 1.0 specification for detailed information.
OHCI REGISTERS FOR USB HOST CONTROLLER Register HcRevision HcControl HcCommonStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCuttentED HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDoneHead HcRmInterval HcFmRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus1 HcRhPortStatus2 Base Address 0x49000000 0x49000004 0x49000008 0x4900000C 0x49000010 0x49000014 0x49000018 0x4900001C 0x49000020 0x49000024 0x49000028 0x4900002C 0x49000030 0x49000034 0x49000038 0x4900003C 0x49000040 0x49000044 0x49000048 0x4900004C 0x49000050 0x49000054 0x49000058 R/W - - - - - - - - - - - - - - - - - - - - - - - Root hub group Frame counter group Memory pointer group Description Control and status group Reset Value - - - - - - - - - - - - - - - - - - - - - - -
12-2
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
USB DEVICE
13
OVERVIEW
USB DEVICE CONTROLLER
Universal Serial Bus (USB) device controller is designed to provide a high performance full speed function controller solution with DMA interface. USB device controller allows bulk transfer with DMA, interrupt transfer and control transfer. USB device controller supports: * Full speed USB device controller compatible with the USB specification version 1.1 * DMA interface for bulk transfer * Five endpoints with FIFO EP0: 16byte (Register) EP1: 128byte IN/OUT FIFO (dual port asynchronous RAM): interrupt or DMA EP2: 128byte IN/OUT FIFO (dual port asynchronous RAM): interrupt or DMA EP3: 128byte IN/OUT FIFO (dual port asynchronous RAM): interrupt or DMA EP4: 128byte IN/OUT FIFO (dual port asynchronous RAM): interrupt or DMA * Integrated USB Transceiver
FEATURE -- Fully compliant with USB Specification Version 1.1 -- Full speed (12Mbps) device -- Integrated USB Transceiver -- Supports control, interrupt and bulk transfer -- Five endpoints with FIFO: One bi-directional control endpoint with 16-byte FIFO (EP0) Four bi-directional bulk endpoints with 128-byte FIFO (EP1, EP2, EP3, and EP4) -- Supports DMA interface for receive and transmit bulk endpoints. (EP1, EP2, EP3, and EP4) -- Independent 128-byte receive and transmit FIFO to maximize throughput -- Supports suspend and remote wakeup function
13-1
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
USB DEVICE
S3C2440X RISC MICROPROCESSOR
MC_ADDR[13:0] RT_VM_IN RT_VP_IN RXD RT_VP_OUT RT_VM_OUT RT_UX_OEN MC_DATA_IN[31:0]
SIU
MC_DATA_OUT[31:0] USB_CLK SYS_CLK
SIE
MCU & DMA I/F
SYS_RESETN MC_WR WR_RDN MC_CSN
GFI
RT_UXSUSPEND
MC_INTR DREQN[3:0] DACKN[3:0]
FIFOs
Figure 13-1. USB Device Controller Block Diagram
13-2
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
USB DEVICE
USB DEVICE CONTROLLER SPECIAL REGISTERS
This section describes detailed functionalities about register sets of USB device controller. All special function register is byte-accessible or word-accessible. If you access byte mode offset-address is different in little endian and big endian. All reserved bit is zero. Common indexed registers depend on INDEX register (INDEX_REG) (offset address: 0X178) value. For example if you want to write EP0 CSR register, you must write `0x00' on the INDEX_REG before writing IN_CSR1 register. NOTE. All register must be resettled after performing Host Reset Signaling.
Register Name NON INDEXED REGISTERS FUNC_ADDR_REG PWR_REG EP_INT_REG (EP0-EP4) USB_INT_REG EP_INT_EN_REG (EP0-EP4) USB_INT_EN_REG FRAME_NUM1_REG FRAME_NUM2_REG INDEX_REG EP0_FIFO_REG EP1_FIFO_REG EP2_FIFO_REG EP3_FIFO_REG EP4_FIFO_REG EP1_DMA_CON EP1_DMA_UNIT EP1_DMA_FIFO EP1_DMA_TTC_L EP1_DMA_TTC_M EP1_DMA_TTC_H
Description Function address register Power management register Endpoint interrupt register USB interrupt register Endpoint interrupt enable register USB Interrupt enable register Frame number 1 register Frame number 2 register Index register Endpoint0 FIFO register Endpoint1 FIFO register Endpoint2 FIFO register Endpoint3 FIFO register Endpoint4 FIFO register Endpoint1 DMA control register Endpoint1 DMA unit counter register Endpoint1 DMA FIFO counter register Endpoint1 DMA transfer counter low-byte register Endpoint1 DMA transfer counter middle-byte register Endpoint1 DMA transfer counter high-byte register
Offset Address 0x140(L) / 0x143(B) 0x144(L) / 0x147(B) 0x148(L) / 0x14B(B) 0x158(L) / 0x15B(B) 0x15C(L) / 0x15F(B) 0x16C(L) / 0x16F(B) 0x170(L) / 0x173(B) 0x174(L) / 0x177(B) 0x178(L) / 0x17B(B) 0x1C0(L) / 0x1C3(B) 0x1C4(L) / 0x1C7(B) 0x1C8(L) / 0x1CB(B) 0x1CC(L) / 0x1CF(B) 0x1D0(L) / 0x1D3(B) 0x200(L) / 0x203(B) 0x204(L) / 0x207(B) 0x208(L) / 0x20B(B) 0x20C(L) / 0x20F(B) 0x210(L) / 0x213(B) 0x214(L) / 0x217(B)
13-3
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
USB DEVICE
S3C2440X RISC MICROPROCESSOR
EP2_DMA_CON EP2_DMA_UNIT EP2_DMA_FIFO EP2_DMA_TTC_L EP2_DMA_TTC_M EP2_DMA_TTC_H EP3_DMA_CON EP3_DMA_UNIT EP3_DMA_FIFO EP3_DMA_TTC_L EP3_DMA_TTC_M EP3_DMA_TTC_H EP4_DMA_CON EP4_DMA_UNIT EP4_DMA_FIFO EP4_DMA_TTC_L EP4_DMA_TTC_M EP4_DMA_TTC_H MAXP_REG IN INDEXED REGISTERS IN_CSR1_REG/EP0_CSR IN_CSR2_REG OUT INDEXED REGISTERS OUT_CSR1_REG OUT_CSR2_REG OUT_FIFO_CNT1_REG OUT_FIFO_CNT2_REG
Endpoint2 DMA control register Endpoint2 DMA unit counter register Endpoint2 DMA FIFO counter register Endpoint2 DMA transfer counter low-byte register Endpoint2 DMA transfer counter middle-byte register Endpoint2 DMA transfer counter high-byte register Endpoint3 DMA control register Endpoint3 DMA unit counter register Endpoint3 DMA FIFO counter register Endpoint3 DMA transfer counter low-byte register Endpoint3 DMA transfer counter middle-byte register Endpoint3 DMA transfer counter high-byte register Endpoint4 DMA control register Endpoint4 DMA unit counter register Endpoint4 DMA FIFO counter register Endpoint4 DMA transfer counter low-byte register Endpoint4 DMA transfer counter middle-byte register Endpoint4 DMA transfer counter high-byte register Endpoint MAX packet register EP In control status register 1/EP0 control status register EP In control status register 2 EP out control status register 1 EP out control status register 2 EP out write count register 1 EP out write count register 2
0x218(L) / 0x21B(B) 0x21C(L) / 0x21F(B) 0x220(L) / 0x223(B) 0x224(L) / 0x227(B) 0x228(L) / 0x22B(B) 0x22C(L) / 0x22F(B) 0x240(L) / 0x243(B) 0x244(L) / 0x247(B) 0x248(L) / 0x24B(B) 0x24C(L) / 0x24F(B) 0x250(L) / 0x253(B) 0x254(L) / 0x247(B) 0x258(L) / 0x25B(B) 0x25C(L) / 0x25F(B) 0x260(L) / 0x263(B) 0x264(L) / 0x267(B) 0x268(L) / 0x26B(B) 0x26C(L) / 0x26F(B) 0x180(L) / 0x183(B) 0x184(L) / 0x187(B) 0x188(L) / 0x18B(B) 0x190(L) / 0x193(B) 0x194(L) / 0x197(B) 0x198(L) / 0x19B(B) 0x19C(L) / 0x19F(B)
COMMON INDEXED REGISTERS
13-4
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
USB DEVICE
FUNCTION ADDRESS REGISTER (FUNC_ADDR_REG) This register maintains the USB device controller address assigned by the host. The Micro Controller Unit (MCU) writes the value received through a SET_ADDRESS descriptor to this register. This address is used for the next token. Register FUNC_ADDR_REG Address 0x52000140(L) 0x52000143(B) R/W R/W (byte) Description Function address register Reset Value 0x00
FUNC_ADDR_REG ADDR_UPDATE
Bit [7]
MCU R /SET
USB R /CLEAR
Description Set by the MCU whenever it updates the FUNCTION_ADDR field in this register. This bit will be cleared by USB when DATA_END bit in EP0_CSR register. The MCU write the unique address, assigned by host, to this field.
Initial State 0
FUNCTION_ADDR
[6:0]
R/W
R
00
13-5
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
USB DEVICE
S3C2440X RISC MICROPROCESSOR
POWER MANAGEMENT REGISTER (PWR_REG) This register acts as a power control register in the USB block. Register PWR_REG Address 0x52000144(L) 0x52000147(B) R/W R/W (byte) Description Power management register Reset Value 0x00
PWR_ADDR Reserved USB_RESET
Bit [7:4] [3]
MCU R
USB SET -
Description
Initial State 0
Set by the USB if reset signaling is received from the host. This bit remains set as long as reset signaling persists on the bus Set by the MCU for MCU Resume. The USB generates the resume signaling during 10ms, if this bit is set in suspend mode. Set by USB automatically when the device enter into suspend mode. It is cleared under the following conditions: 1) The MCU clears the MCU_RESUME bit by writing `0', in order to end remote resume signaling. 2) The resume signal from host is received. Suspend mode enable control bit 0 = Disable (default). The device will not enter suspend mode. 1 = Enable suspend mode
MCU_RESUME
[2]
R/W
R /CLEAR SET /CLEAR
SUSPEND_MODE
[1]
R
0
SUSPEND_EN
[0]
R/W
R
0
13-6
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
USB DEVICE
INTERRUPT REGISTER (EP_INT_REG/USB_INT_REG) The USB core has two interrupt registers. These registers act as status registers for the MCU when it is interrupted. The bits are cleared by writing a `1' (not `0') to each bit that was set. Once the MCU is interrupted, MCU should read the contents of interrupt-related registers and write back to clear the contents if it is necessary. Register EP_INT_REG Address 0x52000148(L) 0x5200014B(B) R/W R/W (byte) Description EP interrupt pending/clear register Reset Value 0x00
EP_INT_REG EP1~EP4 Interrupt
Bit [4:1]
MCU R /CLEAR
USB SET
Description For BULK/INTERRUPT IN endpoints: Set by the USB under the following conditions: 1. IN_PKT_RDY bit is cleared. 2. FIFO is flushed 3. SENT_STALL set. For BULK/INTERRUPT OUT endpoints: Set by the USB under the following conditions: 1. Sets OUT_PKT_RDY bit 2. Sets SENT_STALL bit
Initial State 0
EP0 Interrupt
[0]
R /CLEAR
SET
Correspond to endpoint 0 interrupt. Set by the USB under the following conditions: 1. OUT_PKT_RDY bit is set. 2. IN_PKT_RDY bit is cleared. 3. SENT_STALL bit is set 4. SETUP_END bit is set 5. DATA_END bit is cleared (it indicates the end of control transfer).
0
13-7
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
USB DEVICE
S3C2440X RISC MICROPROCESSOR
Register USB_INT_REG
Address 0x52000158(L) 0x5200015B(B)
R/W R/W (byte)
Description USB interrupt pending/clear register
Reset Value 0x00
USB_INT_REG RESET Interrupt RESUME Interrupt
Bit [2] [1]
MCU R /CLEAR R /CLEAR
USB SET SET
Description Set by the USB when it receives reset signaling. Set by the USB when it receives resume signaling, while in Suspend mode. If the resume occurs due to a USB reset, then the MCU is first interrupted with a RESUME interrupt. Once the clocks resume and the SE0 condition persists for 3ms, USB RESET interrupt will be asserted. Set by the USB when it receives suspend signalizing. This bit is set whenever there is no activity for 3ms on the bus. Thus, if the MCU does not stop the clock after the first suspend interrupt, it will continue to be interrupted every 3ms as long as there is no activity on the USB bus. By default, this interrupt is disabled.
Initial State 0 0
SUSPEND Interrupt
[0]
R /CLEAR
SET
0
13-8
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
USB DEVICE
INTERRUPT ENABLE REGISTER (EP_INT_EN_REG/USB_INT_EN_REG) Corresponding to each interrupt register, The USB device controller also has two interrupt enable registers (except resume interrupt enable). By default, usb reset interrupt is enabled. If bit = 0, the interrupt is disabled. If bit = 1, the interrupt is enabled. Register EP_INT_EN_REG Address 0x5200015C(L) 0x5200015F(B) R/W R/W (byte) Description Determine which interrupt is enabled Reset Value 0xFF
EP_INT_EN_REG EP4_INT_EN EP3_INT_EN EP2_INT_EN EP1_INT_EN EP0_INT_EN
Bit [4] [3] [2] [1] [0]
MCU R/W R/W R/W R/W R/W
USB R R R R R
Description EP4 Interrupt Enable bit 0 = Interrupt disable EP3 Interrupt Enable bit 0 = Interrupt disable EP2 Interrupt Enable bit 0 = Interrupt disable EP1 Interrupt Enable bit 0 = Interrupt disable EP0 Interrupt Enable bit 0 = Interrupt disable
Initial State 1
1 = Enable 1 1 = Enable 1 1 = Enable 1 1 = Enable 1 1 = Enable
13-9
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
USB DEVICE
S3C2440X RISC MICROPROCESSOR
Register USB_INT_EN_REG
Address 0x520016C(L) 0x5200016F(B)
R/W R/W (byte)
Description Determine which interrupt is enabled
Reset Value 0x04
INT_MASK_REG RESET_INT_EN Reserved SUSPEND_INT_EN
Bit [2] [1] [0]
MCU R/W R/W
USB R R
Description Reset interrupt enable bit 0 = Interrupt disable 1 = Enable Suspend interrupt enable bit 0 = Interrupt disable 1 = Enable
Initial State 1 0 0
13-10
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
USB DEVICE
FRAME NUMBER REGISTER (FPAME_NUM1_REG/FRAME_NUM2_REG) When the host transfers USB packets, each Start Of Frame (SOF) packit includes a frame number. The USB device controller catches this frame number and loads it into this register automatically. Register FRAME_NUM1_REG Address 0x52000170(L) 0x52000173(B) R/W R (byte) Description Frame number lower byte register Reset Value 0x00
FRAME_NUM_REG FRAME_NUM1
Bit [7:0]
MCU R
USB W
Description Frame number lower byte value
Initial State 00
Register FRAME_NUM2_REG
Address 0x52000174(L) 0x52000177(B)
R/W R (byte)
Description Frame number higher byte register
Reset Value 0x00
FRAME_NUM_REG FRAME_NUM2
Bit [7:0]
MCU R
USB W
Description Frame number higher byte value
Initial State 00
13-11
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
USB DEVICE
S3C2440X RISC MICROPROCESSOR
INDEX REGISTER (INDEX_REG) The INDEX register is used to indicate certain endpoint registers effectively. The MCU can access the endpoint registers (MAXP_REG, IN_CSR1_REG, IN_CSR2_REG, OUT_CSR1_REG, OUT_CSR2_REG, OUT_FIFO_CNT1_REG, and OUT_FIFO_CNT2_REG) for an endpoint inside the core using the INDEX register.
Register INDEX_REG
Address 0x52000178(L) 0x5200017B(B)
R/W R/W (byte)
Description Register index register
Reset Value 0x00
INDEX_REG INDEX
Bit [7:0]
MCU R/W
USB R
Description Indicate a certain endpoint
Initial State 00
MAX PACKET REGISTER (MAXP_REG) Register MAXP_REG Address 0x52000180(L) 0x52000183(B) R/W R/W (byte) Description End Point MAX packet register Reset Value 0x01
MAXP_REG MAXP
Bit [3:0]
MCU R/W
USB R
Description 0000: Reserved 0001: MAXP = 8 Byte 0010: MAXP = 16 Byte 0100: MAXP = 32 Byte 1000: MAXP = 64 Byte For EP0, MAXP=8 is recommended. For EP1~4, MAXP=64 is recommended. And, if MAXP=64, the dual packet mode will be enabled automatically.
Initial State 0001
13-12
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
USB DEVICE
END POINT0 CONTROL STATUS REGISTER (EP0_CSR) This register has the control and status bits for Endpoint 0. Since a control transaction is involved with both IN and OUT tokens, there is only one CSR register, mapped to the IN CSR1 register. (share IN1_CSR and can access by writing index register "0" and read/write IN1_CSR) Register EP0_CSR Address 0x52000184(L) 0x52000187(B) Bit [7] [6] [5] MCU W W R/W USB CLEAR CLEAR CLEAR R/W R/W (byte) Description Endpoint 0 status register Reset Value 0x00
EP0_CSR SERVICED_SE TUP_END SERVICED_OU T_PKT_RDY SEND_STALL
Description The MCU should write a "1" to this bit to clear SETUP_END. The MCU should write a "1" to this bit to clear OUT_PKT_RDY. MCU should write a "1" to this bit at the same time it clears OUT_PKT_RDY, if it decodes an invalid token. 0 = Finish the STALL condition 1 = The USB issues a STALL and shake to the current control transfer. Set by the USB when a control transfer ends before DATA_END is set. When the USB sets this bit, an interrupt is generated to the MCU. When such a condition occurs, the USB flushes the FIFO and invalidates MCU access to the FIFO. Set by the MCU on the conditions below: 1. After loading the last packet of data into the FIFO, at the same time IN_PKT_RDY is set. 2. While it clears OUT_PKT_RDY after unloading the last packet of data. 3. For a zero length data phase. Set by the USB if a control transaction is stopped due to a protocol violation. An interrupt is generated when this bit is set. The MCU should write "0" to clear this bit. Set by the MCU after writing a packet of data into EP0 FIFO. The USB clears this bit once the packet has been successfully sent to the host. An interrupt is generated when the USB clears this bit, so as the MCU to load the next packet. For a zero length data phase, the MCU sets DATA_END at the same time. Set by the USB once a valid token is written to the FIFO. An interrupt is generated when the USB sets this bit. The MCU clears this bit by writing a "1" to the SERVICED_OUT_PKT_RDY bit.
Initial State 0
0 0
SETUP_END
[4]
R
SET
0
DATA_END
[3]
SET
CLEAR
0
SENT_STALL
[2]
CLE AR SET
SET
0
IN_PKT_RDY
[1]
CLEAR
0
OUT_PKT_RDY
[0]
R
SET
0
13-13
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
USB DEVICE
S3C2440X RISC MICROPROCESSOR
END POINT IN CONTROL STATUS REGISTER (IN_CSR1_REG/IN_CSR2_REG) Register IN_CSR1_REG Address 0x52000184(L) 0x52000187(B) Bit [7] [6] MCU R/W USB R/ CLEAR Used in Set-up procedure. 0: There are alternation of DATA0 and DATA1 1: The data toggle bit is cleared and PID in packet will maintain DATA0 Set by the USB when an IN token issues a STALL handshake, after the MCU sets SEND_STALL bit to start STALL handshaking. When the USB issues a STALL handshake, IN_PKT_RDY is cleared 0: The MCU clears this bit to finish the STALL condition. 1: The MCU issues a STALL handshake to the USB. Set by the MCU if it intends to flush the packet in Input-related FIFO. This bit is cleared by the USB when the FIFO is flushed. The MCU is interrupted when this happens. If a token is in process, the USB waits until the transmission is complete before FIFO flushing. If two packets are loaded into the FIFO, only first packet (The packet is intended to be sent to the host) is flushed, and the corresponding IN_PKT_RDY bit is cleared Set by the MCU after writing a packet of data into the FIFO. The USB clears this bit once the packet has been successfully sent to the host. An interrupt is generated when the USB clears this bit, so the MCU can load the next packet. While this bit is set, the MCU will not be able to write to the FIFO. If the MCU sets SEND STALL bit, this bit cannot be set. R/W R/W (byte) Description IN END POINT control status register1 Reset Value 0x00
IN_CSR1_REG Reserved CLR_DATA_ TOGGLE
Description
Initial State 0 0
SENT_STALL
[5]
R/ CLEAR
SET
0
SEND_STALL
[4]
W/R
R
0
FIFO_FLUSH
[3]
R/W
CLEAR
0
Reserved IN_PKT_RDY
[2:1] [0
R/SET
CLEAR
0 0
13-14
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
USB DEVICE
Register IN_CSR2_REG
Address 0x52000188(L) 0x5200018B(B) Bit [7] MCU R/W USB R
R/W R/W (byte)
Description IN END POINT control status register2
Reset Value 0x20
IN_CSR2_REG AUTO_SET
Description If set, whenever the MCU writes MAXP data, IN_PKT_RDY will automatically be set by the core without any intervention from MCU. If the MCU writes less than MAXP data, IN_PKT_RDY bit has to be set by the MCU. Used only for endpoints whose transfer type is programmable. 1: Reserved 0: Configures endpoint to Bulk mode Used only for endpoints whose direction is programmable. 1: Configures Endpoint Direction as IN 0: Configures Endpoint Direction as OUT Determine whether the interrupt should be issued or not, when the EP1 IN_PKT_RDY condition happens. This is only useful for DMA mode. 0 = Interrupt enable, 1 = Interrupt Disable -
Initial State 0
ISO
[6]
R/W
R
0
MODE_IN
[5]
R/W
R
1
IN_DMA_INT_EN
[4]
R/W
R
0
Reserved
[3:0]
-
-
-
13-15
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
USB DEVICE
S3C2440X RISC MICROPROCESSOR
END POINT OUT CONTROL STATUS REGISTER (OUT_CSR1_REG/OUT_CSR2_REG) Register OUT_CSR1_REG Address 0x52000190(L) 0x52000193(B) R/W R/W (byte) Description End Point out control status register1 Reset Value 0x00
OUT_CSR1_REG CLR_DATA_TOGGLE SENT_STALL
Bit [7] [6]
MCU R/W CLEAR /R
USB CLEAR SET
Description When the MCU writes a 1 to this bit, the data toggle sequence bit is reset to DATA0. Set by the USB when an OUT token is ended with a STALL handshake. The USB issues a stall handshake to the host if it sends more than MAXP data for the OUT TOKEN. 0: The MCU clears this bit to end the STALL condition handshake, IN PKT RDY is cleared. 1: The MCU issues a STALL handshake to the USB. The MCU clears this bit to end the STALL condition handshake, IN PKT RDY is cleared. The MCU writes a 1 to flush the FIFO. This bit can be set only when OUT_PKT_RDY (D0) is set. The packet due to be unloaded by the MCU will be flushed. Set by the USB after it has loaded a packet of data into the FIFO. Once the MCU reads the packet from FIFO, this bit should be cleared by MCU (write a "0").
Initial State 0 0
SEND_STALL
[5]
R/W
R
0
FIFO_FLUSH
[4]
R/W
CLEAR
0
Reserved OUT_PKT_RDY
[3:1] [0]
R/ CLEAR
SET
0 0
13-16
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
USB DEVICE
Register OUT_CSR2_REG
Address 0x52000194(L) 0x52000197(B)
R/W R/W (byte)
Description End Point out control status register2
Reset Value 0x00
OUT_CSR2_REG AUTO_CLR
Bit [7]
MCU R/W
USB R
Description If the MCU is set, whenever the MCU reads data from the OUT FIFO, OUT_PKT_RDY will automatically be cleared by the logic without any intervention from the MCU. Determine endpoint transfer type. 0: Configures endpoint to Bulk mode. 1: Reserved. Determine whether the interrupt should be issued or not. OUT_PKT_RDY condition happens. This is only useful for DMA mode 0 = Interrupt Enable 1 = Interrupt Disable
Initial State 0
ISO
[6]
R/W
R
0
OUT_DMA_INT_MAS K
[5]
R/W
R
0
13-17
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
USB DEVICE
S3C2440X RISC MICROPROCESSOR
END POINT OUT WRITE COUNT REGISTER (OUT_FIFO_CNT1_REG/OUT_FIFO_CNT2_REG) These registers maintain the number of bytes in the packet as the number is unloaded by the MCU. Register OUT_FIFO_CNT1_REG Address 0x52000198(L) 0x5200019B(B) R/W R (byte) Description End Point out write count register1 Reset Value 0x00
OUT_FIFO_CNT1_REG OUT_CNT_LOW
Bit [7:0]
MCU R
USB W
Description Lower byte of write count
Initial State 0x00
Register OUT_FIFO_CNT2_REG
Address 0x5200019C(L) 0x5200019F(B)
R/W R (byte)
Description End Point out write count register2
Reset Value 0x00
OUT_FIFO_CNT2_REG OUT_CNT_HIGH
Bit [7:0]
MCU R
USB W
Description Higher byte of write count. The OUT_CNT_HIGH may be always 0 normally.
Initial State 0x00
END POINT FIFO REGISTER (EPN_FIFO_REG) The EPn_FIFO_REG enables the MCU to access to the EPn FIFO. Register EP0_FIFO EP1_FIFO EP2_FIFO EP3_FIFO EP4_FIFO Address 0x520001C0(L) 0x520001C3 (B) 0x520001C4(L) 0x520001C7(B) 0x520001C8(L) 0x520001CB(B) 0x520001CC(L) 0x520001CF(B) 0x520001D0(L) 0x520001D3(B) R/W R/W (byte) R/W (byte) R/W (byte) R/W (byte) R/W (byte) Description End Point0 FIFO register End Point1 FIFO register End Point2 FIFO register End Point3 FIFO register End Point4 FIFO register Reset Value 0xXX 0xXX 0xXX 0xXX 0xXX
EPn_FIFO FIFO_DATA
Bit [7:0]
MCU R/W
USB R/W
Description FIFO data value
Initial State 0xXX
13-18
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
USB DEVICE
DMA INTERFACE CONTROL REGISTER (EPN_DMA_CON) Register EP1_DMA_CON EP2_DMA_CON EP3_DMA_CON EP4_DMA_CON Address 0x52000200(L) 0x52000203(B) 0x52000218(L) 0x5200021B(B) 0x52000240(L) 0x52000243(B) 0x52000258(L) 0x5200025B(B) R/W R/W (byte) R/W (byte) R/W (byte) R/W (byte) Description EP1 DMA interface control register EP2 DMA interface control register EP3 DMA interface control register EP4 DMA interface control register Reset Value 0x00 0x00 0x00 0x00
EPn_DMA_CON RUN_OB
Bit [7]
MCU R/W
USB W
Description Read) DMA Run Observation 0: DMA is stopped 1:DMA is running Write) Ignore EPn_DMA_TTC_n register 0: DMA requests will be stopped if EPn_DMA_TTC_n reaches 0. 1: DMA requests will be continued although EPn_DMA_TTC_n reaches 0. DMA State Monitoring DMA Demand mode enable bit 0: Demand mode disable 1: Demand mode enable Functionally separated into write and read operation. Write operation: `0' = Stop `1' = Run Read operation: OUT DMA Run Observation Start DMA operation. 0 = Stop 1 = Run
Initial State 0
STATE DEMAND_MODE
[6:4] [3]
R R/W
W R
0 0
OUT_RUN_OB / OUT_DMA_RUN IN_DMA_RUN DMA_MODE_EN
[2]
R/W
R/W
0
[1] [0]
R/W R/W
R R/Clear
0 0
Set DMA mode.If the RUN_OB has been wrtten as 0 and EPn_DMA_TTC_n reaches 0, DMA_MODE_EN bit will be cleared by USB. 0 = Interrupt Mode 1 = DMA Mode
13-19
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
USB DEVICE
S3C2440X RISC MICROPROCESSOR
DMA UNIT COUNTER REGISTER (EPN_DMA_UNIT) This register is valid in Demand mode. In other modes, this register value must be set to `0x01' Register EP1_DMA_UNIT EP2_DMA_UNIT EP3_DMA_UNIT EP4_DMA_UNIT Address 0x52000204(L) 0x52000207(B) 0x5200021C(L) 0x5200021F(B) 0x52000244(L) 0x52000247(B) 0x5200025C(L) 0x5200025F(B) R/W R/W (byte) R/W (byte) R/W (byte) R/W (byte) Description EP1 DMA transfer unit counter base register EP2 DMA transfer unit counter base register EP3 DMA transfer unit counter base register EP4 DMA transfer unit counter base register Reset Value 0x00 0x00 0x00 0x00
DMA_UNIT EPn_UNIT_CNT
Bit [7:0]
MCU R/W
USB R
Description EP DMA transfer unit counter value
Initial State 0x00
13-20
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
USB DEVICE
DMA FIFO COUNTER REGISTER (EPN_DMA_FIFO) This register has values in byte size in FIFO to be transferred by DMA. In case of OUT_DMA_RUN enabled, the value in OUT FIFO Write Count Register1 will be loaded in this register automatically. In case of IN DMA mode, the MCU should set proper value by software. Register EP1_DMA_FIFO EP2_DMA_FIFO EP3_DMA_FIFO EP4_DMA_FIFO Address 0x52000208(L) 0x5200020B(B) 0x52000220(L) 0x52000223(B) 0x52000248(L) 0x5200024B(B) 0x52000260(L) 0x52000263(B) R/W R/W (byte) R/W (byte) R/W (byte) R/W (byte) Description EP1 DMA transfer FIFO counter base register EP2 DMA transfer FIFO counter base register EP3 DMA transfer FIFO counter base register EP4 DMA transfer FIFO counter base register Reset Value 0x00 0x00 0x00 0x00
DMA_FIFO EPn_FIFO_CNT
Bit [7:0]
MCU R/W
USB R
Description EP DMA transfer FIFO counter value
Initial State 0x00
13-21
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
USB DEVICE
S3C2440X RISC MICROPROCESSOR
DMA TOTAL TRANSFER COUNTER REGISTER (EPn_DMA_TTC_L,M,H) This register should have total number of bytes to be transferred using DMA (total 20-bit counter). Register EP1_DMA_TTC_L EP1_DMA_TTC_M EP1_DMA_TTC_H EP2_DMA_TTC_L EP2_DMA_TTC_M EP2_DMA_TTC_H EP3_DMA_TTC_L EP3_DMA_TTC_M EP3_DMA_TTC_H EP4_DMA_TTC_L EP4_DMA_TTC_M EP4_DMA_TTC_H Address 0x5200020C(L) 0x5200020F(B) 0x52000210(L) 0x52000213(B) 0x52000214(L) 0x52000217(B) 0x52000224(L) 0x52000227(B) 0x52000228(L) 0x5200022B(B) 0x5200022C(L) 0x5200022F(B) 0x5200024C(L) 0x5200024F(B) 0x52000250(L) 0x52000253(B) 0x52000254(L) 0x52000257(B) 0x52000264(L) 0x52000267(B) 0x52000268(L) 0x5200026B(B) 0x5200026C(L) 0x5200026F(B) R/W R/W (byte) R/W (byte) R/W (byte) R/W (byte) R/W (byte) R/W (byte) R/W (byte) R/W (byte) R/W (byte) R/W (byte) R/W (byte) R/W (byte) Description EP1 DMA total transfer counter(lower byte) EP1 DMA total transfer counter(middle byte) EP1 DMA total transfer counter(higher byte) EP2 DMA total transfer counter(lower byte) EP2 DMA total transfer counter(middle byte) EP2 DMA total transfer counter(higher byte) EP3 DMA total transfer counter(lower byte) EP3 DMA total transfer counter(middle byte) EP3 DMA total transfer counter(higher byte) EP4 DMA total transfer counter(lower byte) EP4 DMA total transfer counter(middle byte) EP4 DMA total transfer counter(higher byte) Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
DMA_TX EPn_TTC_L EPn_TTC_M EPn_TTC_H
Bit [7:0] [7:0] [3:0]
MCU R/W R/W R/W
USB R R R
Description DMA total transfer count value (lower byte) DMA total transfer count value (middle byte) DMA total transfer count value (higher byte)
Initial State 0x00 0x00 0x00
13-22
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
INTERRUPT CONTROLLER
14
OVERVIEW
INTERRUPT CONTROLLER
The interrupt controller in the S3C2440X receives the request from 59 interrupt sources. These interrupt sources are provided by internal peripherals such as the DMA controller, the UART, IIC, and others. In these interrupt sources, the UARTn and EINTn interrupts are 'OR'ed to the interrupt controller. When receiving multiple interrupt requests from internal peripherals and external interrupt request pins, the interrupt controller requests FIQ or IRQ interrupt of the ARM920T core after the arbitration procedure. The arbitration procedure depends on the hardware priority logic and the result is written to the interrupt pending register, which helps users notify which interrupt is generated out of various interrupt sources.
Request sources (with sub -register)
SUBSRCPND
SUBMASK
SRCPND
MASK
INTPND
Priority Request sources (without sub -register) MODE
IRQ
FIQ LCD interrupt has different features. Please see the chapter 15 LCD Controller
Figure 14-1. Interrupt Process Diagram
14-1
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
INTERRUPT CONTROLLER
S3C2440X RISC MICROPROCESSOR
INTERRUPT CONTROLLER OPERATION F-bit and I-bit of Program Status Register (PSR) If the F-bit of PSR in ARM920T CPU is set to 1, the CPU does not accept the Fast Interrupt Request (FIQ) from the interrupt controller. Likewise, If I-bit of the PSR is set to 1, the CPU does not accept the Interrupt Request (IRQ) from the interrupt controller. So, the interrupt controller can receive interrupts by clearing F-bit or I-bit of the PSR to 0 and setting the corresponding bit of INTMSK to 0. Interrupt Mode The ARM920T has two types of Interrupt mode: FIQ or IRQ. All the interrupt sources determine which mode is used at interrupt request. Interrupt Pending Register The S3C2440X has two interrupt pending resisters: source pending register (SRCPND) and interrupt pending register (INTPND). These pending registers indicate whether or not an interrupt request is pending. When the interrupt sources request interrupt service, the corresponding bits of SRCPND register are set to 1, and at the same time, only one bit of the INTPND register is set to 1 automatically after arbitration procedure. If interrupts are masked, the corresponding bits of the SRCPND register are set to 1. This does not cause the bit of INTPND register changed. When a pending bit of the INTPND register is set, the interrupt service routine starts whenever the I-flag or F-flag is cleared to 0. The SRCPND and INTPND registers can be read and written, so the service routine must clear the pending condition by writing a 1 to the corresponding bit in the SRCPND register first and then clear the pending condition in the INTPND registers by using the same method. Interrupt Mask Register This register indicates that an interrupt has been disabled if the corresponding mask bit is set to 1. If an interrupt mask bit of INTMSK is 0, the interrupt will be serviced normally. If the corresponding mask bit is 1 and the interrupt is generated, the source pending bit will be set.
14-2
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
INTERRUPT CONTROLLER
INTERRUPT SOURCES The interrupt controller supports 59 interrupt sources as shown in the table below. Sources INT_ADC INT_RTC INT_SPI1 INT_UART0 INT_IIC INT_USBH INT_USBD INT_NFCON INT_UART1 INT_SPI0 INT_SDI INT_DMA3 INT_DMA2 INT_DMA1 INT_DMA0 INT_LCD INT_UART2 INT_TIMER4 INT_TIMER3 INT_TIMER2 INT_TIMER1 INT_TIMER0 INT_WDT INT_TICK nBATT_FLT INT_CAM EINT8_23 EINT4_7 EINT3 EINT2 EINT1 EINT0 Descriptions ADC EOC and Touch interrupt (INT_ADC/INT_TC) RTC alarm interrupt SPI1 interrupt UART0 Interrupt (ERR, RXD, and TXD) IIC interrupt USB Host interrupt USB Device interrupt Nand Flash Control Interrupt UART1 Interrupt (ERR, RXD, and TXD) SPI0 interrupt SDI interrupt DMA channel 3 interrupt DMA channel 2 interrupt DMA channel 1 interrupt DMA channel 0 interrupt LCD interrupt (INT_FrSyn and INT_FiCnt) UART2 Interrupt (ERR, RXD, and TXD) Timer4 interrupt Timer3 interrupt Timer2 interrupt Timer1 interrupt Timer0 interrupt Watch-Dog timer interrupt RTC Time tick interrupt Battery Fault interrupt Camera Interface (INT_CAM_S, INT_CAM_C) External interrupt 8 - 23 External interrupt 4 - 7 External interrupt 3 External interrupt 2 External interrupt 1 External interrupt 0 Arbiter Group ARB5 ARB5 ARB5 ARB5 ARB4 ARB4 ARB4 ARB4 ARB4 ARB4 ARB 3 ARB3 ARB3 ARB3 ARB3 ARB3 ARB2 ARB2 ARB2 ARB2 ARB 2 ARB2 ARB1 ARB1 ARB1 ARB1 ARB1 ARB1 ARB0 ARB0 ARB0 ARB0
14-3
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
INTERRUPT CONTROLLER
S3C2440X RISC MICROPROCESSOR
INTERRUPT PRIORITY GENERATING BLOCK The priority logic for 32 interrupt requests is composed of seven rotation based arbiters: six first-level arbiters and one second-level arbiter as shown in Figure 14-1 below.
ARM IRQ
ARBITER6
REQ0 REQ1 REQ2 REQ3 REQ4 REQ5
ARBITER0
REQ1/EINT0 REQ2/EINT1 REQ3/EINT2 REQ4/EINT3
ARBITER1
REQ0/EINT4_7 REQ1/EINT8_23 REQ2/INT_CAM REQ3/nBATT_FLT REQ4/INT_TICK REQ5/INT_WDT
ARBITER2
REQ0/INT_TIMER0 REQ1/INT_TIMER1 REQ2/INT_TIMER2 REQ3/INT_TIMER3 REQ4/INT_TIMER4 REQ5/INT_UART2
ARBITER3
REQ0/INT_LCD REQ1/INT_DMA0 REQ2/INT_DMA1 REQ3/INT_DMA2 REQ4/INT_DMA3 REQ5/INT_SDI
ARBITER4
REQ0/INT_SPI0 REQ1/INT_UART1 REQ2/INT_NFCON REQ3/INT_USBD REQ4/INT_USBH REQ5/INT_IIC
ARBITER5
REQ1/INT_UART0 REQ2/INT_SPI1 REQ3/INT_RTC REQ4/INT_ADC
Figure 14-2. Priority Generating Block
14-4
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
INTERRUPT CONTROLLER
INTERRUPT PRIORITY Each arbiter can handle six interrupt requests based on the one bit arbiter mode control (ARB_MODE) and two bits of selection control signals (ARB_SEL) as follows: If ARB_SEL bits are 00b, the priority order is REQ0, REQ1, REQ2, REQ3, REQ4, and REQ5. If ARB_SEL bits are 01b, the priority order is REQ0, REQ2, REQ3, REQ4, REQ1, and REQ5. If ARB_SEL bits are 10b, the priority order is REQ0, REQ3, REQ4, REQ1, REQ2, and REQ5. If ARB_SEL bits are 11b, the priority order is REQ0, REQ4, REQ1, REQ2, REQ3, and REQ5. Note that REQ0 of an arbiter always has the highest priority, and REQ5 has the lowest one. In addition, by changing the ARB_SEL bits, we can rotate the priority of REQ1 to REQ4. Here, if ARB_MODE bit is set to 0, ARB_SEL bits are not automatically changed, making the arbiter to operate in the fixed priority mode (note that even in this mode, we can reconfigure the priority by manually changing the ARB_SEL bits). On the other hand, if ARB_MODE bit is 1, ARB_SEL bits are changed in rotation fashion, e.g., if REQ1 is serviced, ARB_SEL bits are changed to 01b automatically so as to put REQ1 into the lowest priority. The detailed rules of ARB_SEL change are as follows: If REQ0 or REQ5 is serviced, ARB_SEL bits are not changed at all. If REQ1 is serviced, ARB_SEL bits are changed to 01b. If REQ2 is serviced, ARB_SEL bits are changed to 10b. If REQ3 is serviced, ARB_SEL bits are changed to 11b. If REQ4 is serviced, ARB_SEL bits are changed to 00b.
14-5
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
INTERRUPT CONTROLLER
S3C2440X RISC MICROPROCESSOR
INTERRUPT CONTROLLER SPECIAL REGISTERS
There are five control registers in the interrupt controller: source pending register, interrupt mode register, mask register, priority register, and interrupt pending register. All the interrupt requests from the interrupt sources are first registered in the source pending register. They are divided into two groups including Fast Interrupt Request (FIQ) and Interrupt Request (IRQ), based on the interrupt mode register. The arbitration procedure for multiple IRQs is based on the priority register. SOURCE PENDING (SRCPND) REGISTER The SRCPND register is composed of 32 bits each of which is related to an interrupt source. Each bit is set to 1 if the corresponding interrupt source generates the interrupt request and waits for the interrupt to be serviced. Accordingly, this register indicates which interrupt source is waiting for the request to be serviced. Note that each bit of the SRCPND register is automatically set by the interrupt sources regardless of the masking bits in the INTMASK register. In addition, the SRCPND register is not affected by the priority logic of interrupt controller. In the interrupt service routine for a specific interrupt source, the corresponding bit of the SRCPND register has to be cleared to get the interrupt request from the same source correctly. If you return from the ISR without clearing the bit, the interrupt controller operates as if another interrupt request came in from the same source. In other words, if a specific bit of the SRCPND register is set to 1, it is always considered as a valid interrupt request waiting to be serviced. The time to clear the corresponding bit depends on the user's requirement. If you want to receive another valid request from the same source, you should clear the corresponding bit first, and then enable the interrupt. You can clear a specific bit of the SRCPND register by writing a data to this register. It clears only the bit positions of the SRCPND corresponding to those set to one in the data. The bit positions corresponding to those that are set to 0 in the data remains as they are. Register SRCPND Address 0X4A000000 R/W R/W Description Indicate the interrupt request status. 0 = The interrupt has not been requested. 1 = The interrupt source has asserted the interrupt request. Reset Value 0x00000000
14-6
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
INTERRUPT CONTROLLER
SRCPND INT_ADC INT_RTC INT_SPI1 INT_UART0 INT_IIC INT_USBH INT_USBD INT_NFCON INT_UART1 INT_SPI0 INT_SDI INT_DMA3 INT_DMA2 INT_DMA1 INT_DMA0 INT_LCD INT_UART2 INT_TIMER4 INT_TIMER3 INT_TIMER2 INT_TIMER1 INT_TIMER0 INT_WDT INT_TICK nBATT_FLT INT_CAM EINT8_23 EINT4_7 EINT3 EINT2 EINT1 EINT0
Bit [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested,
Description 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested
Initial State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
14-7
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
INTERRUPT CONTROLLER
S3C2440X RISC MICROPROCESSOR
. INTERRUPT MODE (INTMOD) REGISTER This register is composed of 32 bits each of which is related to an interrupt source. If a specific bit is set to 1, the corresponding interrupt is processed in the FIQ (fast interrupt) mode. Otherwise, it is processed in the IRQ mode (normal interrupt). Note that only one interrupt source can be serviced in the FIQ mode in the interrupt controller (you should use the FIQ mode only for the urgent interrupt). Thus, only one bit of INTMOD can be set to 1. Register INTMOD Address 0X4A000004 R/W R/W 0 = IRQ mode Description Interrupt mode regiseter. 1 = FIQ mode Reset Value 0x00000000
Note: If an interrupt mode is set to FIQ mode in the INTMOD register, FIQ interrupt will not affect both INTPND and INTOFFSET registers. In this case, the two registers are valid only for IRQ mode interrupt source.
14-8
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
INTERRUPT CONTROLLER
INTMOD INT_ADC INT_RTC INT_SPI1 INT_UART0 INT_IIC INT_USBH INT_USBD INT_NFCON INT_URRT1 INT_SPI0 INT_SDI INT_DMA3 INT_DMA2 INT_DMA1 INT_DMA0 INT_LCD INT_UART2 INT_TIMER4 INT_TIMER3 INT_TIMER2 INT_TIMER1 INT_TIMER0 INT_WDT INT_TICK nBATT_FLT INT_CAM EINT8_23 EINT4_7 EINT3 EINT2 EINT1 EINT0
Bit [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ
Description
Initial State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
14-9
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
INTERRUPT CONTROLLER
S3C2440X RISC MICROPROCESSOR
INTERRUPT MASK (INTMSK) REGISTER This register also has 32 bits each of which is related to an interrupt source. If a specific bit is set to 1, the CPU does not service the interrupt request from the corresponding interrupt source (note that even in such a case, the corresponding bit of SRCPND register is set to 1). If the mask bit is 0, the interrupt request can be serviced. Register INTMSK Address 0X4A000008 R/W R/W Description Determine which interrupt source is masked. The masked interrupt source will not be serviced. 0 = Interrupt service is available. 1 = Interrupt service is masked. Reset Value 0xFFFFFFFF
14-10
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
INTERRUPT CONTROLLER
INTMSK INT_ADC INT_RTC INT_SPI1 INT_UART0 INT_IIC INT_USBH INT_USBD INT_NFCON INT_UART1 INT_SPI0 INT_SDI INT_DMA3 INT_DMA2 INT_DMA1 INT_DMA0 INT_LCD INT_UART2 INT_TIMER4 INT_TIMER3 INT_TIMER2 INT_TIMER1 INT_TIMER0 INT_WDT INT_TICK nBATT_FLT INT_CAM EINT8_23 EINT4_7 EINT3 EINT2 EINT1 EINT0
Bit [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
Description 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked
Initial State 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
14-11
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
INTERRUPT CONTROLLER
S3C2440X RISC MICROPROCESSOR
PRIORITY REGISTER (PRIORITY) Register Address R/W R/W Description IRQ priority control register Reset Value 0x7F
PRIORITY 0x4A00000C
PRIORITY ARB_SEL6
Bit [20:19]
Description Arbiter 6 group priority order set 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 Arbiter 5 group priority order set 00 = REQ 1-2-3-4 01 = REQ 2-3-4-1 10 = REQ 3-4-1-2 11 = REQ 4-1-2-3 Arbiter 4 group priority order set 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 Arbiter 3 group priority order set 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 Arbiter 2 group priority order set 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 Arbiter 1 group priority order set 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 Arbiter 0 group priority order set 00 = REQ 1-2-3-4 01 = REQ 2-3-4-1 10 = REQ 3-4-1-2 11 = REQ 4-1-2-3 Arbiter 6 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Arbiter 5 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Arbiter 4 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Arbiter 3 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Arbiter 2 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Arbiter 1 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Arbiter 0 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable
Initial State 0
ARB_SEL5
[18:17]
0
ARB_SEL4
[16:15]
0
ARB_SEL3
[14:13]
0
ARB_SEL2
[12:11]
0
ARB_SEL1
[10:9]
0
ARB_SEL0
[8:7]
0
ARB_MODE6 ARB_MODE5 ARB_MODE4 ARB_MODE3 ARB_MODE2 ARB_MODE1 ARB_MODE0
[6] [5] [4] [3] [2] [1] [0]
1 1 1 1 1 1 1
14-12
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
INTERRUPT CONTROLLER
INTERRUPT PENDING (INTPND) REGISTER Each of the 32 bits in the interrupt pending register shows whether the corresponding interrupt request, which is unmasked and waits for the interrupt to be serviced, has the highest priority . Since the INTPND register is located after the priority logic, only one bit can be set to 1, and that interrupt request generates IRQ to CPU. In interrupt service routine for IRQ, you can read this register to determine which interrupt source is serviced among the 32 sources. Like the SRCPND register, this register has to be cleared in the interrupt service routine after clearing the SRCPND register. We can clear a specific bit of the INTPND register by writing a data to this register. It clears only the bit positions of the INTPND register corresponding to those set to one in the data. The bit positions corresponding to those that are set to 0 in the data remains as they are. Register INTPND Address 0X4A000010 R/W R/W Description Indicate the interrupt request status. 0 = The interrupt has not been requested. 1 = The interrupt source has asserted the interrupt request. Reset Value 0x00000000
Note: If the FIQ mode interrupt occurs, the corresponding bit of INTPND will not be turned on as the INTPND register is available only for IRQ mode interrupt.
14-13
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
INTERRUPT CONTROLLER
S3C2440X RISC MICROPROCESSOR
INTPND INT_ADC INT_RTC INT_SPI1 INT_UART0 INT_IIC INT_USBH INT_USBD INT_NFCON INT_UART1 INT_SPI0 INT_SDI INT_DMA3 INT_DMA2 INT_DMA1 INT_DMA0 INT_LCD INT_UART2 INT_TIMER4 INT_TIMER3 INT_TIMER2 INT_TIMER1 INT_TIMER0 INT_WDT INT_TICK nBATT_FLT INT_CAM EINT8_23 EINT4_7 EINT3 EINT2 EINT1 EINT0
Bit [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested,
Description 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested
Initial State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
14-14
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
INTERRUPT CONTROLLER
INTERRUPT OFFSET (INTOFFSET) REGISTER The value in the interrupt offset register shows which interrupt request of IRQ mode is in the INTPND register. This bit can be cleared automatically by clearing SRCPND and INTPND. Register INTOFFSET Address 0X4A000014 R/W R Description Indicate the IRQ interrupt request source Reset Value 0x00000000
INT Source INT_ADC INT_RTC INT_SPI1 INT_UART0 INT_IIC INT_USBH INT_USBD INT_NFCON INT_UART1 INT_SPI0 INT_SDI INT_DMA3 INT_DMA2 INT_DMA1 INT_DMA0 INT_LCD
The OFFSET value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INT Source INT_UART2 INT_TIMER4 INT_TIMER3 INT_TIMER2 INT_TIMER1 INT_TIMER0 INT_WDT INT_TICK nBATT_FLT INT_CAM EINT8_23 EINT4_7 EINT3 EINT2 EINT1 EINT0
The OFFSET value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Note: FIQ mode interrupt does not affect the INTOFFSET register as the register is available only for IRQ mode interrupt.
14-15
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
INTERRUPT CONTROLLER
S3C2440X RISC MICROPROCESSOR
SUB SOURCE PENDING (SUBSRCPND) REGISTER You can clear a specific bit of the SUBSRCPND register by writing a data to this register. It clears only the bit positions of the SUBSRCPND register corresponding to those set to one in the data. The bit positions corresponding to those that are set to 0 in the data remains as they are. Register SUBSRCPND Address 0X4A000018 R/W R/W Description Indicate the interrupt request status. 0 = The interrupt has not been requested. 1 = The interrupt source has asserted the interrupt request. Reset Value 0x00000000
SUBSRCPND Reserved INT_CAM_C INT_CAM_S INT_ADC INT_TC INT_ERR2 INT_TXD2 INT_RXD2 INT_ERR1 INT_TXD1 INT_RXD1 INT_ERR0 INT_TXD0 INT_RXD0
Bit [31:13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Not used 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested,
Description 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested
Initial State 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Map To SRCPND SRCPND INT_UART0 INT_UART1 INT_UART2 INT_ADC INT_CAM SUBSRCPND INT_RXD0,INT_TXD0,INT_ERR0 INT_RXD1,INT_TXD1,INT_ERR1 INT_RXD2,INT_TXD2,INT_ERR2 INT_ADC, INT_TC INT_CAM_S, INT_CAM_C Remark
14-16
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
INTERRUPT CONTROLLER
INTERRUPT SUB MASK (INTSUBMSK) REGISTER This register has 11 bits each of which is related to an interrupt source. If a specific bit is set to 1, the interrupt request from the corresponding interrupt source is not serviced by the CPU (note that even in such a case, the corresponding bit of the SUBSRCPND register is set to 1). If the mask bit is 0, the interrupt request can be serviced. Register INTSUBMSK Address 0X4A00001C R/W R/W Description Determine which interrupt source is masked. The masked interrupt source will not be serviced. 0 = Interrupt service is available. 1 = Interrupt service is masked. Reset Value 0xFFFF
INTSUBMSK Reserved Reserved INT_CAM_C INT_CAM_S INT_ADC INT_TC INT_ERR2 INT_TXD2 INT_RXD2 INT_ERR1 INT_TXD1 INT_RXD1 INT_ERR0 INT_TXD0 INT_RXD0
Bit [31:16] [15:13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Not used Not used
Description
Initial State 0 0x7
0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available,
1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked
1 1 1 1 1 1 1 1 1 1 1 1 1
14-17
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
INTERRUPT CONTROLLER
S3C2440X RISC MICROPROCESSOR
NOTES
14-18
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
LCD CONTROLLER
15
OVERVIEW
LCD CONTROLLER
The LCD controller in the S3C2440X consists of the logic for transferring LCD image data from a video buffer located in system memory to an external LCD driver. The LCD controller supports monochrome, 2-bit per pixel (4-level gray scale) or 4-bit per pixel (16-level gray scale) mode on a monochrome LCD, using a time-based dithering algorithm and Frame Rate Control (FRC) method and it can be interfaced with a color LCD panel at 8-bit per pixel (256-level color) and 12-bit per pixel (4096-level color) for interfacing with STN LCD. It can support 1-bit per pixel, 2-bit per pixel, 4-bit per pixel, and 8-bit per pixel for interfacing with the palettized TFT color LCD panel, and 16-bit per pixel and 24-bit per pixel for non-palettized true-color display. The LCD controller can be programmed to support different requirements on the screen related to the number of horizontal and vertical pixels, data line width for the data interface, interface timing, and refresh rate. FEATURES STN LCD displays: -- Supports 3 types of LCD panels: 4-bit dual scan, 4-bit single scan, and 8-bit single scan display type -- Supports the monochrome, 4 gray levels, and 16 gray levels -- Supports 256 colors and 4096 colors for color STN LCD panel -- Supports multiple screen size Typical actual screen size: 640 x 480, 320 x 240, 160 x 160, and others Maximum virtual screen size is 4Mbytes. Maximum virtual screen size in 256 color mode: 4096 x 1024, 2048 x 2048, 1024 x 4096, and others TFT LCD displays: -- Supports 1, 2, 4 or 8-bpp (bit per pixel) palettized color displays for TFT -- Supports 16-bpp non-palettized true-color displays for color TFT -- Supports 24-bpp non-palettized true-color displays for color TFT -- Supports maximum 16M color TFT at 24bit per pixel mode -- Supports multiple screen size Typical actual screen size: 640 x 480, 320 x 240, 160 x 160, and others Maximum virtual screen size is 4Mbytes. Maximum virtual screen size in 64K color mode: 2048 x 1024 and others
15-1
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
LCD CONTROLLER
S3C2440X RISC MICROPROCESSOR
COMMON FEATURES The LCD controller has a dedicated DMA that supports to fetch the image data from video buffer located in system memory. Its features also include: -- Dedicated interrupt functions (INT_FrSyn and INT_FiCnt) -- The system memory is used as the display memory. -- Supports Multiple Virtual Display Screen (Supports Hardware Horizontal/Vertical Scrolling) -- Programmable timing control for different display panels -- Supports little and big-endian byte ordering, as well as WinCE data formats -- Supports 2-type SEC TFT LCD panel (SAMSUNG 3.5" Portrait / 256K Color /Reflective and Transflective a-Si TFT LCD) LTS350Q1-PD1: TFT LCD panel with touch panel and front light unit (Reflective type) LTS350Q1-PD2: TFT LCD panel only LTS350Q1-PE1: TFT LCD panel with touch panel and front light unit (Transflective type) LTS350Q1-PE2: TFT LCD panel only NOTE WinCE doesn't support the 12-bit packed data format. Please check if WinCE can support the 12-bit color-mode. EXTERNAL INTERFACE SIGNAL STN VFRAME (Frame sync. Signal) VLINE (Line sync pulse signal) VCLK (Pixel clock signal) VD[23:0] (LCD pixel data output ports) VM (AC bias signal for LCD driver) LCD_PWREN TFT VSYNC (Vertical sync. Signal) HSYNC (Horizontal sync. Signal) VCLK (Pixel clock signal) VD[23:0] (LCD pixel data output ports) VDEN (Data enable signal) LEND (Line end signal) LCD_PWREN SEC TFT (LTS350Q1-PD1/2) STV CPV LCD_HCLK VD[23:0] TP STH LCD_PWREN LPC_OE LPC_REV LPC_REVB SEC TFT (LTS350Q1-PE1/2) STV CPV LCD_HCLK VD[23:0] TP STH LCD_PWREN LCC_INV LCC_REV LCC_REVB
15-2
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
LCD CONTROLLER
BLOCK DIAGRAM
System Bus REGBANK TIMEGEN VCLK /LCD_HCLK VLINE / HSYNC / CPV VFRAME / VSYNC / STV VM / VDEN / TP . . . LCD_LPCOE / LCD_LCCINV LCD_LPCREV / LCD_LCCREV LCD_LPCREVB / LCD_LCCREVB VD[23:0]
LPC3600
VIDEO MUX
LCC3600 LCDCDMA
VIDPRCS
LPC3600 is a timing control logic unit for LTS350Q1-PD1 or LTS350Q1-PD2. LCC3600 is a timing control logic unit for LTS350Q1-PE1 or LTS350Q1-PE2.
Figure 15-1. LCD Controller Block Diagram
The S3C2440X LCD controller is used to transfer the video data and to generate the necessary control signals, such as VFRAME, VLINE, VCLK, VM, and so on. In addition to the control signals, the S3C2440X has the data ports for video data, which are VD[23:0] as shown in Figure 15-1. The LCD controller consists of a REGBANK, LCDCDMA, VIDPRCS, TIMEGEN, and LPC3600 (See the Figure 15-1 LCD Controller Block Diagram). The REGBANK has 17 programmable register sets and 256x16 palette memory which are used to configure the LCD controller. The LCDCDMA is a dedicated DMA, which can transfer the video data in frame memory to LCD driver automatically. By using this special DMA, the video data can be displayed on the screen without CPU intervention. The VIDPRCS receives the video data from the LCDCDMA and sends the video data through the VD[23:0] data ports to the LCD driver after changing them into a suitable data format, for example 4/8-bit single scan or 4-bit dual scan display mode. The TIMEGEN consists of programmable logic to support the variable requirements of interface timing and rates commonly found in different LCD drivers. The TIMEGEN block generates VFRAME, VLINE, VCLK, VM, and so on. The description of data flow is as follows: FIFO memory is present in the LCDCDMA. When FIFO is empty or partially empty, the LCDCDMA requests data fetching from the frame memory based on the burst memory transfer mode (consecutive memory fetching of 4 words (16 bytes) per one burst request without allowing the bus mastership to another bus master during the bus transfer). When the transfer request is accepted by bus arbitrator in the memory controller, there will be four successive word data transfers from system memory to internal FIFO. The total size of FIFO is 28 words, which consists of 12 words FIFOL and 16 words FIFOH, respectively. The S3C2440X has two FIFOs to support the dual scan display mode. In case of single scan mode, one of the FIFOs (FIFOH) can only be used.
15-3
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
LCD CONTROLLER
S3C2440X RISC MICROPROCESSOR
STN LCD CONTROLLER OPERATION
TIMING GENERATOR (TIMEGEN) The TIMEGEN generates the control signals for the LCD driver, such as VFRAME, VLINE, VCLK, and VM. These control signals are closely related to the configuration on the LCDCON1/2/3/4/5 registers in the REGBANK. Based on these programmable configurations on the LCD control registers in the REGBANK, the TIMEGEN can generate the programmable control signals suitable to support many different types of LCD drivers. The VFRAME pulse is asserted for the duration of the entire first line at a frequency of once per frame. The VFRAME signal is asserted to bring the LCD's line pointer to the top of the display to start over. The VM signal helps the LCD driver alternate the polarity of the row and column voltages, which are used to turn the pixel on and off. The toggling rate of VM signals depends on the MMODE bit of the LCDCON1 register and MVAL field of the LCDCON4 register. If the MMODE bit is 0, the VM signal is configured to toggle on every frame. If the MMODE bit is 1, the VM signal is configured to toggle on the every event of the elapse of the specified number of VLINE by the MVAL[7:0] value. Figure 15-4 shows an example for MMODE=0 and for MMODE=1 with the value of MVAL[7:0]=0x2. When MMODE=1, the VM rate is related to MVAL[7:0], as shown below: VM Rate = VLINE Rate / ( 2 x MVAL) The VFRAME and VLINE pulse generation relies on the configurations of the HOZVAL field and the LINEVAL field in the LCDCON2/3 register. Each field is related to the LCD size and display mode. In other words, the HOZVAL and LINEVAL can be determined by the size of the LCD panel and the display mode according to the following equation: HOZVAL = (Horizontal display size / Number of the valid VD data line)-1 In color mode: Horizontal display size = 3 x Number of Horizontal Pixel In the 4-bit single scan display mode, the Number of valid VD data line should be 4. In case of 4-bit dual scan display, the Number of valid VD data lineshould also be 4 while in case of 8-bit single scan display mode, the Number of valid VD data line should be 8. LINEVAL = (Vertical display size) -1: In case of single scan display type LINEVAL = (Vertical display size / 2) -1: In case of dual scan display type The rate of VCLK signal depends on the configuration of the CLKVAL field in the LCDCON1 register. Table 15-1 defines the relationship of VCLK and CLKVAL. The minimum value of CLKVAL is 2. VCLK(Hz)=HCLK/(CLKVAL x 2) The frame rate is the VFRAM signal frequency. The frame rate is closely related to the field of WLH[1:0](VLINE pulse width) WDLY[1:0] (the delay width of VCLK after VLINE pulse), HOZVAL, LINEBLANK, and LINEVAL in the LCDCON1/2/3/4 registers as well as VCLK and HCLK. Most LCD drivers need their own adequate frame rate. The frame rate is calculated as follows: frame_rate(Hz) = 1 / [ { (1/VCLK) x (HOZVAL+1)+(1/HCLK) x (A+B+(LINEBLANK x 8) ) } x ( LINEVAL+1) ]
A = 2(4+WLH), B = 2(4+WDLY)
15-4
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
LCD CONTROLLER
Table 15-1. Relation between VCLK and CLKVAL (STN, HCLK=60MHz) CLKVAL 2 3 : 1023 60MHz/X 60 MHz/4 60 MHz/6 : 60 MHz/2046 VCLK 15.0 MHz 10.0 MHz : 29.3 kHz
VIDEO OPERATION The S3C2440X LCD controller supports 8-bit color mode (256 color mode), 12-bit color mode (4096 color mode), 4 level gray scale mode, 16 level gray scale mode as well as the monochrome mode. For the gray or color mode, it is required to implement the shades of gray level or color according to time-based dithering algorithm and Frame Rate Control (FRC) method. The selection can be made following a programmable lockup table, which will be explained later. The monochrome mode bypasses these modules (FRC and lookup table) and basically serializes the data in FIFOH (and FIFOL if a dual scan display type is used) into 4-bit (or 8-bit if a 4-bit dual scan or 8-bit single scan display type is used) streams by shifting the video data to the LCD driver. The following sections describe the operation on the gray and color mode in terms of the lookup table and FRC. Lookup Table The S3C2440X can support the lookup table for various selection of color or gray level mapping, ensuring flexible operation for users. The lookup table is the palette which allows the selection on the level of color or gray (Selection on 4-gray levels among 16 gray levels in case of 4 gray mode, selection on 8 red levels among 16 levels, 8 green levels among 16 levels and 4 blue levels among 16 levels in case of 256 color mode). In other words, users can select 4 gray levels among 16 gray levels by using the lookup table in the 4 gray level mode. The gray levels cannot be selected in the 16 gray level mode; all 16 gray levels must be chosen among the possible 16 gray levels. In case of 256 color mode, 3 bits are allocated for red, 3 bits for green and 2 bits for blue. The 256 colors mean that the colors are formed from the combination of 8 red, 8 green and 4 blue levels (8x8x4 = 256). In the color mode, the lookup table can be used for suitable selections. Eight red levels can be selected among 16 possible red levels, 8 green levels among 16 green levels, and 4 blue levels among 16 blue levels. In case of 4096 color mode, there is no selection as in the 256 color mode. Gray Mode Operation The S3C2440X LCD controller supports two gray modes: 2-bit per pixel gray (4 level gray scale) and 4-bit per pixel gray (16 level gray scale). The 2-bit per pixel gray mode uses a lookup table (BLUELUT), which allows selection on 4 gray levels among 16 possible gray levels. The 2-bit per pixel gray lookup table uses the BULEVAL[15:0] in Blue Lookup Table (BLUELUT) register as same as blue lookup table in color mode. The gray level 0 will be denoted by BLUEVAL[3:0] value. If BLUEVAL[3:0] is 9, level 0 will be represented by gray level 9 among 16 gray levels. If BLUEVAL[3:0] is 15, level 0 will be represented by gray level 15 among 16 gray levels, and so on. Following the same method as above, level 1 will also be denoted by BLUEVAL[7:4], the level 2 by BLUEVAL[11:8], and the level 3 by BLUEVAL[15:12]. These four groups among BLUEVAL[15:0] will represent level 0, level 1, level 2, and level 3. In 16 gray levels, there is no selection as in the 16 gray levels.
15-5
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
LCD CONTROLLER
S3C2440X RISC MICROPROCESSOR
256 Level Color Mode Operation The S3C2440X LCD controller can support an 8-bit per pixel 256 color display mode. The color display mode can generate 256 levels of color using the dithering algorithm and FRC. The 8-bit per pixel are encoded into 3-bits for red, 3-bits for green, and 2-bits for blue. The color display mode uses separate lookup tables for red, green, and blue. Each lookup table uses the REDVAL[31:0] of REDLUT register, GREENVAL[31:0] of GREENLUT register, and BLUEVAL[15:0] of BLUELUT register as the programmable lookup table entries. Similar to the gray level display, 8 group or field of 4 bits in the REDLUR register, i.e., REDVAL[31:28], REDLUT[27:24], REDLUT[23:20], REDLUT[19:16], REDLUT[15:12], REDLUT[11:8], REDLUT[7:4], and REDLUT[3:0], are assigned to each red level. The possible combination of 4 bits (each field) is 16, and each red level should be assigned to one level among possible 16 cases. In other words, the user can select the suitable red level by using this type of lookup table. For green color, the GREENVAL[31:0] of the GREENLUT register is assigned as the lookup table, as was done in the case of red color. Similarly, the BLUEVAL[15:0] of the BLUELUT register is also assigned as a lookup table. For blue color, 2 bits are allocated for 4 blue levels, different from the 8 red or green levels. 4096 Level Color Mode Operation The S3C2440X LCD controller can support a 12-bit per pixel 4096 color display mode. The color display mode can generate 4096 levels of color using the dithering algorithm and FRC. The 12-bit per pixel are encoded into 4-bits for red, 4-bits for green, and 4-bits for blue. The 4096 color display mode does not use lookup tables.
15-6
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
LCD CONTROLLER
DITHERING AND FRAME RATE CONTROL For STN LCD displays (except monochrome), video data must be processed by a dithering algorithm. The DITHFRC block has two functions, such as Time-based Dithering Algorithm for reducing flicker and Frame Rate Control (FRC) for displaying gray and color level on the STN panel. The main principle of gray and color level display on the STN panel based on FRC is described. For example, to display the third gray (3/16) level from a total of 16 levels, the 3 times pixel should be on and 13 times pixel off. In other words, 3 frames should be selected among the 16 frames, of which 3 frames should have a pixel-on on a specific pixel while the remaining 13 frames should have a pixel-off on a specific pixel. These 16 frames should be displayed periodically. This is basic principle on how to display the gray level on the screen, so-called gray level display by FRC. The actual example is shown in th Table 15-2. To represent the 14 gray level in the table, we should have a 6/7 duty cycle, which mean that there are 6 times pixel-on and one time pixel-off. The other cases for all gray levels are also shown in Table 15-2. In the STN LCD display, we should be reminded of one item, i.e., Flicker Noise due to the simultaneous pixel-on and -off on adjacent frames. For example, if all pixels on first frame are turned on and all pixels on next frame are turned off, the Flicker Noise will be maximized. To reduce the Flicker Noise on the screen, the average probability of pixel-on and -off between frames should be the same. In order to realize this, the Time-based Dithering Algorithm, which varies the pattern of adjacent pixels on every frame, should be used. This is explained in detail. th For the 16 gray level, FRC should have the following relationship between gray level and FRC. The 15 gray level th should always have pixel-on, and the 14 gray level should have 6 times pixel-on and one times pixel-off, and the th th 13 gray level should have 4 times pixel-on and one times pixel-off, ,,,,,,,, , and the 0 gray level should always have pixel-off as shown in Table 15-2. Table 15-2. Dither Duty Cycle Examples Pre-dithered Data (gray level number) 15 14 13 12 11 10 9 8 1 6/7 4/5 3/4 5/7 2/3 3/5 4/7 Duty Cycle Pre-dithered Data (gray level number) 7 6 5 4 3 2 1 0 1/2 3/7 2/5 1/3 1/4 1/5 1/7 0 Duty Cycle
15-7
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
LCD CONTROLLER
S3C2440X RISC MICROPROCESSOR
Display Types The LCD controller supports 3 types of LCD drivers: 4-bit dual scan, 4-bit single scan, and 8-bit single scan display mode. Figure 15-2 shows these 3 different display types for monochrome displays, and Figure 15-3 show these 3 different display types for color displays. 4-bit Dual Scan Display Type A 4-bit dual scan display uses 8 parallel data lines to shift data to both the upper and lower halves of the display at the same time. The 4 bits of data in the 8 parallel data lines are shifted to the upper half and 4 bits of data is shifted to the lower half, as shown in Figure 15-2. The end of frame is reached when each half of the display has been shifted and transferred. The 8 pins (VD[7:0]) for the LCD output from the LCD controller can be directly connected to the LCD driver. 4-bit Single Scan Display Type A 4-bit single scan display uses 4 parallel data lines to shift data to successive single horizontal lines of the display at a time, until the entire frame has been shifted and transferred. The 4 pins (VD[3:0]) for the LCD output from the LCD controller can be directly connected to the LCD driver, and the 4 pins (VD[7:4]) for the LCD output are not used. 8-bit Single Scan Display Type An 8-bit single scan display uses 8 parallel data lines to shift data to successive single horizontal lines of the display at a time, until the entire frame has been shifted and transferred. The 8 pins (VD[7:0]) for the LCD output from the LCD controller can be directly connected to the LCD driver. 256 Color Displays Color displays require 3 bits (Red, Green, and Blue) of image data per pixel, and so the number of horizontal shift registers for each horizontal line corresponds to three times the number of pixels of one horizontal line. resulting in a horizontal shift register of length 3 times the number of pixels per horizontal line This RGB is shifted to the LCD driver as consecutive bits via the parallel data lines. Figure 15-3 shows the RGB and order of the pixels in the parallel data lines for the 3 types of color displays. 4096 Color Displays Color displays require 3 bits (Red, Green, and Blue) of image data per pixel, and so the number of horizontal shift registers for each horizontal line corresponds to three times the number of pixels of one horizontal line. This RGB is shifted to the LCD driver as consecutive bits via the parallel data lines. This RGB order is determined by the sequence of video data in video buffers.
15-8
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
LCD CONTROLLER
MEMORY DATA FORMAT (STN, BSWP=0) Mono 4-bit Dual Scan Display: Video Buffer Memory: Address 0000H 0004H * * * 1000H 1004H * * * L[31:0] M[31:0] Data A[31:0] B[31:0]
LCD Panel A[31] A[30] ...... A[0] B[31] B[30] ...... B[0] ......
L[31] L[30] ...... L[0] M[31] M[30] ...... M[0] ......
LCD Panel
Mono 4-bit Single Scan Display & 8-bit Single Scan Display: Video Buffer Memory: Address 0000H 0004H 0008H * * * Data A[31:0] B[31:0] C[31:0]
A[31] A[30] A[29] ...... A[0] B[31] B[30] ...... B[0] C[31] ...... C[0] ......
15-9
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
LCD CONTROLLER
S3C2440X RISC MICROPROCESSOR
MEMORY DATA FORMAT ( STN, BSWP=0 ) (CONTINUED) In 4-level gray mode, 2 bits of video data correspond to 1 pixel. In 16-level gray mode, 4 bits of video data correspond to 1 pixel. In 256 level color mode, 8 bits (3 bits of red, 3 bits of green, and 2 bits of blue) of video data correspond to 1 pixel. The color data format in a byte is as follows: Bit [ 7:5 ] Red Bit [ 4:2 ] Green Bit[1:0] Blue
In 4096 level color mode, 12 bits (4 bits of red, 4 bits of green, 4 bits of blue) of video data correspond to 1 pixel. The following table shows color data format in words: (Video data must reside at 3 word boundaries (8 pixel), as follows) RGB order DATA Word #1 Word #2 Word #3 [31:28] Red( 1) Blue(3) Green(6) [27:24] Green(1) Red(4) Blue(6) [23:20] Blue( 1) Green(4) Red(7) [19:16] Red( 2) Blue(4) Green(7) [15:12] Green( 2) Red(5) Blue(7) [11:8] Blue( 2) Green(5) Red(8) [7:4] Red(3) Blue(5) Green(8) [3:0] Green(3) Red(6) Blue(8)
15-10
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
LCD CONTROLLER
VD3
VD2
VD1
VD0
VD3
VD2
VD1
VD0
.
.
.
.
.
.
VD3
VD2
VD1
VD0
VD3
VD2
VD1
VD0
.
.
.
.
.
.
4-bit Dual Scan Display VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 . . . . . .
4-bit Single Scan Display VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 . . . . . .
8-bit Single Scan Display
Figure 15-2. Monochrome Display Types (STN)
15-11
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
LCD CONTROLLER
S3C2440X RISC MICROPROCESSOR
VD3 R1
VD2 G1 1 Pixel
VD1 B1
VD0 R2
VD3 G2
VD2 B2
VD1 R3
VD0 G3
. . . . . .
VD7 R1
VD6 G1
VD5 B1
VD4 R2
VD7 G2
VD6 B2
VD5 R3
VD4 G3
4-bit Dual Scan Display
. . . . . .
VD3 R1
VD2 G1 1 Pixel
VD1 B1
VD0 R2
VD3 G2
VD2 B2
VD1 R3
VD0 G3
4-bit Single Scan Display
. . . . . .
VD7 R1
VD6 G1 1 Pixel
VD5 B1
VD4 R2
VD3 G2
VD2 B2
VD1 R3
VD0 G3
8-bit Single Scan Display
Figure 15-3. Color Display Types (STN)
. . . . . .
15-12
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
LCD CONTROLLER
Timing Requirements Image data should be transferred from the memory to the LCD driver using the VD[7:0] signal. VCLK signal is used to clock the data into the LCD driver's shift register. After each horizontal line of data has been shifted into the LCD driver's shift register, the VLINE signal is asserted to display the line on the panel. The VM signal provides an AC signal for the display. The LCD uses the signal to alternate the polarity of the row and column voltages, which are used to turn the pixels on and off, because the LCD plasma tends to deteriorate whenever subjected to a DC voltage. It can be configured to toggle on every frame or to toggle every programmable number of VLINE signals. Figure 15-4 shows the timing requirements for the LCD driver interface.
15-13
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
LCD CONTROLLER
S3C2440X RISC MICROPROCESSOR
Full Frame Timing(MMODE = 0)
INT_FrSyn VFRAME VM VLINE LINE1LINE2LINE3LINE4LINE5LINE6 LINEn LINE1
Full Frame Timing(MMODE = 1, MVAL=0x2)
INT_FrSyn VFRAME VM VLINE LINE1LINE2LINE3LINE4LINE5LINE6 LINEn LINE1
INT_FrSyn First Line Timing VFRAME VM VLINE LINECNT VCLK WDLY First Line Check & Data Timing VFRAME VM VLINE VCLK VD[7:0] WDLY WLH LINEBLANK WDLY Display the last line of the previous frame LINECNT decreases & Display the 1st line
Figure 15-4. 8-bit Single Scan Display Type STN LCD Timing
15-14
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
LCD CONTROLLER
TFT LCD CONTROLLER OPERATION
The TIMEGEN generates the control signals for LCD driver, such as VSYNC, HSYNC, VCLK, VDEN, and LEND signal. These control signals are highly related with the configurations on the LCDCON1/2/3/4/5 registers in the REGBANK. Base on these programmable configurations on the LCD control registers in the REGBANK, the TIMEGEN can generate the programmable control signals suitable for the support of many different types of LCD drivers. The VSYNC signal is asserted to cause the LCD's line pointer to start over at the top of the display. The VSYNC and HSYNC pulse generation depends on the configurations of both the HOZVAL field and the LINEVAL field in the LCDCON2/3 registers. The HOZVAL and LINEVAL can be determined by the size of the LCD panel according to the following equations: HOZVAL = (Horizontal display size) -1 LINEVAL = (Vertical display size) -1 The rate of VCLK signal depends on the CLKVAL field in the LCDCON1 register. Table 15-3 defines the relationship of VCLK and CLKVAL. The minimum value of CLKVAL is 0. VCLK(Hz)=HCLK/[(CLKVAL+1)x2] The frame rate is VSYNC signal frequency. The frame rate is related with the field of VSYNC, VBPD, VFPD, LINEVAL, HSYNC, HBPD, HFPD, HOZVAL, and CLKVAL in LCDCON1 and LCDCON2/3/4 registers. Most LCD drivers need their own adequate frame rate. The frame rate is calculated as follows: Frame Rate = 1/ [ { (VSPW+1) + (VBPD+1) + (LIINEVAL + 1) + (VFPD+1) } x {(HSPW+1) + (HBPD +1) + (HFPD+1) + (HOZVAL + 1) } x { 2 x ( CLKVAL+1 ) / ( HCLK ) } ]
Table 15-3. Relation between VCLK and CLKVAL (TFT, HCLK=60MHz) CLKVAL 1 2 : 1023 VIDEO OPERATION The TFT LCD controller within the S3C2440X supports 1, 2, 4 or 8 bpp (bit per pixel) palettized color displays and 16 or 24 bpp non-palettized true-color displays. 256 Color Palette The S3C2440X can support the 256 color palette for various selection of color mapping, providing flexible operation for users. 60MHz/X 60 MHz/4 60 MHz/6 : 60 MHz/2048 VCLK 15.0 MHz 10.0 MHz : 30.0 kHz
15-15
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
LCD CONTROLLER
S3C2440X RISC MICROPROCESSOR
MEMORY DATA FORMAT (TFT) This section includes some examples of each display mode. 24BPP Display (BSWP = 0, HWSWP = 0, BPP24BL = 0) D[31:24] 000H 004H 008H ... Dummy Bit Dummy Bit Dummy Bit D[23:0] P1 P2 P3
(BSWP = 0, HWSWP = 0, BPP24BL = 1) D[31:8] 000H 004H 008H ... P1 P2 P3 D[7:0] Dummy Bit Dummy Bit Dummy Bit
P1
P2
P3
P4
P5
......
LCD Panel
VD Pin Descriptions at 24BPP VD RED GREEN BLUE 23 22 21 20 7 6 5 4 19 18 17 16 15 14 13 12 11 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 10 9 8 7 6 5 4 3 2 1 0
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
LCD CONTROLLER
16BPP Display (BSWP = 0, HWSWP = 0) D[31:16] 000H 004H 008H ... P1 P3 P5 D[15:0] P2 P4 P6
(BSWP = 0, HWSWP = 1) D[31:16] 000H 004H 008H ... P2 P4 P6 D[15:0] P1 P3 P5
P1
P2
P3
P4
P5
......
LCD Panel
VD Pin Descriptions at 16BPP (5:6:5) VD RED GREEN BLUE (5:5:5:I) VD RED GREEN 23 22 21 20 19 18 17 16 15 14 13 12 11 10 4 3 2 1 0 I NC 4 3 2 1 0 I 4 3 2 1 0 I 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 4 3 2 1 0 NC 5 4 3 2 1 0 4 3 2 1 0 9 8 7 6 5 4 3 2 1 NC 0
NC
NC
NC
BLUE NOTE : The unused VD pins can be used as GPIO
15-17
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
LCD CONTROLLER
S3C2440X RISC MICROPROCESSOR
8BPP Display (BSWP = 0, HWSWP = 0) D[31:24] D[23:16] 000H 004H 008H ... P1 P5 P9 P2 P6 P10 D[15:8] P3 P7 P11 D[7:0] P4 P8 P12
(BSWP = 1, HWSWP = 0) D[31:24] D[23:16] 000H 004H 008H ... P4 P8 P12 P3 P7 P11 D[15:8] P2 P6 P10 D[7:0] P1 P5 P9
P1
P2
P3
P4
P5
P6
P7
P8
P9 P10 P11 P12 ......
LCD Panel
15-18
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
LCD CONTROLLER
4BPP Display (BSWP = 0, HWSWP = 0) D[31:28] 000H 004H 008H ... P1 P9 P17 D[27:24] P2 P10 P18 D[23:20] P3 P11 P19 D[19:16] P4 P12 P20 D[15:12] P5 P13 P21 D[11:8] P6 P14 P22 D[7:4] P7 P15 P23 D[3:0] P8 P16 P24
(BSWP = 1, HWSWP = 0) D[31:28] 000H 004H 008H ... P7 P15 P23 D[27:24] P8 P16 P24 D[23:20] P5 P13 P21 D[19:16] P6 P14 P22 D[15:12] P3 P11 P19 D[11:8] P4 P12 P20 D[7:4] P1 P9 P17 D[3:0] P2 P10 P18
2BPP Display (BSWP = 0, HWSWP = 0) D 000H 004H 008H ... [31:30] P1 P17 P33 [29:28] P2 P18 P34 [27:26] P3 P19 P35 [25:24] P4 P20 P36 [23:22] P5 P21 P37 [21:20] P6 P22 P38 [19:18] P7 P23 P39 [17:16] P8 P24 P40
D 000H 004H 008H ...
[15:14] P9 P25 P41
[13:12] P10 P26 P42
[11:10] P11 P27 P43
[9:8] P12 P28 P44
[7:6] P13 P29 P45
[5:4] P14 P30 P46
[3:2] P15 P31 P47
[1:0] P16 P32 P48
15-19
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
LCD CONTROLLER
S3C2440X RISC MICROPROCESSOR
256 PALETTE USAGE (TFT) Palette Configuration and Format Control The S3C2440X provides 256 color palette for TFT LCD Control. The user can select 256 colors from the 64K colors in these two formats. The 256 color palette consists of the 256 (depth) x 16-bit SPSRAM. The palette supports 5:6:5 (R:G:B) format and 5:5:5:1(R:G:B:I) format. When the user uses 5:5:5:1 format, the intensity data(I) is used as a common LSB bit of each RGB data. So, 5:5:5:1 format is the same as R(5+I):G(5+I):B(5+I) format. In 5:5:5:1 format, for example, the user can write the palette as in Table 15-5 and then connect VD pin to TFT LCD panel(R(5+I)=VD[23:19]+VD[18], VD[10] or VD[2], G(5+I)=VD[15:11]+ VD[18], VD[10] or VD[2], B(5+I)=VD[7:3]+ VD[18], VD[10] or VD[2].), and set FRM565 of LCDCON5 register to 0. Table 15-4. 5:6:5 Format INDEX\Bit Pos. 00H 01H ....... FFH Number of VD R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 23 22 21 20 19 15 14 13 12 11 10 7 6 5 4 3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1)
Address 0X4D000400 ....... 0X4D0007FC 0X4D000404
R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
Table 15-5. 5:5:5:1 Format INDEX\Bit Pos. 00H 01H ....... FFH Number of VD R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 23 22 21 20 19 15 14 13 12 11 7 6 5 4 3 I
2)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0 I I
Address 0X4D000400 0X4D000404 ....... 0X4D0007FC
R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
Notes: 1. 0x4D000400 is Palette start address. 2. VD18, VD10 and VD2 have the same output value, I. 3. DATA[31:16] is invalid.
Palette Read/Write When the user performs Read/Write operation on the palette, HSTATUS and VSTATUS of LCDCON5 register must be checked, for Read/Write operation is prohibited during the ACTIVE status of HSTATUS and VSTATUS. Temporary Palette Configuration The S3C2440X allows the user to fill a frame with one color without complex modification to fill the one color to the frame buffer or palette. The one colored frame can be displayed by the writing a value of the color which is displayed on LCD panel to TPALVAL of TPAL register and enable TPALEN.
15-20
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
LCD CONTROLLER
A[31] A[30] A[29] A[28] A[27] A[26]A[25] A[24] A[23] A[22] A[21] A[20] A[19]A[18] A[17] A[16] R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 R4 B3 B2 B1 B0 I
1
2
3
4
5
R4
R3
R2
R1
R0
G4
G3
G2
G1
G0 A[6]
R4
B3
B2
B1
B0
I
A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[7]
A[5] A[4] A[3] A[2] A[1] A[0]
LCD Panel 16BPP 5:5:5+1 Format(Non-Palette)
A[31] A[30] A[29] A[28] A[27] A[26]A[25] A[24] A[23] A[22] A[21] A[20] A[19]A[18] A[17] A[16] R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
1
2
3
4
5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
A[15] A[14] A[13] A[12]A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] LCD Panel 16BPP 5:6:5 Format(Non-Palette)
Figure 15-5. 16BPP Display Types (TFT)
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
LCD CONTROLLER
S3C2440X RISC MICROPROCESSOR
INT_FrSyn
VSYNC
HSYNC
VDEN
VBPD+1 VSPW+1
LINEVAL +1 1 Frame
VFPD+1
1 Line
HSYNC
VCLK
VD
VDEN
LEND HBPD+1 HSPW+1
HOZVAL+1
HFPD+1
Figure 15-6. TFT LCD Timing Example
15-22
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
LCD CONTROLLER
SAMSUNG TFT LCD PANEL (3.5" PORTRAIT / 256K COLOR / REFLECTIVE A-SI/TRANSFLECTIVE A-SI TFT LCD) The S3C2440X supports following SEC TFT LCD panels. 1. SAMSUNG 3.5" Portrait / 256K Color /Reflective a-Si TFT LCD. LTS350Q1-PD1: TFT LCD panel with touch panel and front light unit LTS350Q1-PD2: TFT LCD panel only 2. SAMSUNG 3.5" Portrait / 256K Color /Transflective a-Si TFT LCD. LTS350Q1-PE1: TFT LCD panel with touch panel and front light unit LTS350Q1-PE2: TFT LCD panel only The S3C2440X provides timing signals as follows to use LTS350Q1-PD1 / PD2 and LTS350Q1-PE1 / PE2 LTS350Q1-PD1 / PD2 STH: Horizontal Start Pulse TP: Source Driver Data Load Pulse INV: Digital Data Inversion LCD_HCLK: Horizontal Sampling Clock CPV: Vertical Shift Clock STV: Vertical Start Pulse OE: Gate On Enable REV: Inversion Signal REVB: Inversion Signal LTS350Q1-PE1 / PE2 STH: Horizontal Start Pulse TP: Source Driver Data Load Pulse INV: Digital Data Inversion LCD_HCLK: Horizontal Sampling Clock CPV: Vertical Shift Clock STV: Vertical Start Pulse LCCINV: Source drive IC sampling inversion signal REV: VCOM modulation Signal REVB: Inversion Signal
So, LTS350Q1-PD1/2 and PE1/2 can be connected with the S3C2440X without using the additional timing control logic. But the user should additionally apply Vcom generator circuit, various voltages, INV signal and Gray scale voltage generator circuit, which is recommended by PRODUCT INFORMATION (SPEC) of LTS350Q1-PD1/2 and PE1/2. Detailed timing diagram is also described in PRODUCT INFORMATION (SPEC) of LTS350Q1-PD1/2 and PE1/2. Refer to the documentation (PRODUCT INFORMATION of LTS350Q1-PD1/2 and PE1/2), which is prepared by AMLCD Technical Customer Center of Samsung Electronics Co., LTD.
CAUTION: The S3C2440X has HCLK, working as the clock of AHB bus. Accidentally, SEC TFT LCD panel (LTS350Q1-PD1/2 and PE1/2) has Horizontal Sampling Clock (HCLK). These two HCLKs may cause a confusion. So, note that HCLK of the S3C2440X is HCLK and other HCLK of the LTS350 is LCD_HCLK. Check that the HCLK of SEC TFT LCD panel (LTS350Q1-PD1/2 and PE1/2) is changed to LCD_HCLK.
15-23
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
LCD CONTROLLER
S3C2440X RISC MICROPROCESSOR
VIRTUAL DISPLAY (TFT/STN) The S3C2440X supports hardware horizontal or vertical scrolling. If the screen is scrolled, the fields of LCDBASEU and LCDBASEL in LCDSADDR1/2 registers need to be changed (see Figure 15-8), except the values of PAGEWIDTH and OFFSIZE. The video buffer in which the image is stored should be larger than the LCD panel screen in size.
OFFSIZE
PAGEWIDTH
OFFSIZE
This is the data of line 1 of virtual screen. This is the data of line 1 of virtual screen. This is the data of line 2 of virtual screen. This is the data of line 2 of virtual screen. This is the data of line 3 of virtual screen. This is the data of line 3 of virtual screen. This is the data of line 4 of virtual screen. This is the data of line 4 of virtual screen. This is the data of line 5 of virtual screen. This is the data of line 5 of virtual screen. This is the data of line 6 of virtual screen. This is the data of line 6 of virtual screen. This is the data of line 7 of virtual screen. This is the data of line 7 of virtual screen. This is the data of line 8 of virtual screen. This is the data of line 8 of virtual screen. This is the data of line 9 of virtual screen. This is the data of line 9 of virtual screen. This is the data of line 10 of virtual screen. This is the data of line 10 of virtual screen. This is the data of line 11 of virtual screen. This is the data of line 11 of virtual screen. LCDBASEU View Port (The same size of LCD panel.) LINEVAL + 1
LCDBASEL
This is the data of line 1 of virtual screen. This is the data of line 1 of virtual screen. This is the data of line 2 of virtual screen. This is the data of line 2 of virtual screen. This is the data of line 3 of virtual screen. This is the data of line 3 of virtual screen. This is the data of line 4 of virtual screen. This is the data of line 4 of virtual screen. This is the data of line 5 of virtual screen. This is the data of line 5 of virtual screen. This is the data of line 6 of virtual screen. This is the data of line 6 of virtual screen. This is the data of line 7 of virtual screen. This is the data of line 7 of virtual screen. This is the data of line 8 of virtual screen. This is the data of line 8 of virtual screen. This is the data of line 9 of virtual screen. This is the data of line 9 of virtual screen. This is the data of line 10 of virtual screen. This is the data of line 10 of virtual screen. This is the data of line 11 of virtual screen. This is the data of line 11 of virtual screen.
Figure 15-7. Example of Scrolling in Virtual Display (Single Scan)
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
. . . . . .
Before Scrolling
After Scrolling
2003.09.25
S3C2440X RISC MICROPROCESSOR
LCD CONTROLLER
LCD POWER ENABLE (STN/TFT) The S3C2440X provides Power enable (PWREN) function. When PWREN is set to make PWREN signal enabled, the output value of LCD_PWREN pin is controlled by ENVID. In other words, If LCD_PWREN pin is connected to the power on/off control pin of the LCD panel, the power of LCD panel is controlled by the setting of ENVID automatically. The S3C2440X also supports INVPWREN bit to invert polarity of the PWREN signal. This function is available only when LCD panel has its own power on/off control port and when port is connected to LCD_PWREN pin.
ENVID LCD_PWREN
LCD Panel On
VFRAME
VLINE
STN LCD
ENVID
LCD_PWREN
LCD Panel On
VSYNC
HSYNC
VDEN
1 FRAME
TFT LCD
Figure 15-8. Example of PWREN function (PWREN=1, INVPWREN=0)
15-25
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
LCD CONTROLLER
S3C2440X RISC MICROPROCESSOR
LCD CONTROLLER SPECIAL REGISTERS LCD Control 1 Register Register LCDCON1 Address 0X4D000000 R/W R/W Description LCD control 1 register Reset Value 0x00000000
LCDCON1 LINECNT (read only) CLKVAL
Bit [27:18] [17:8]
Description Provide the status of the line counter. Down count from LINEVAL to 0 Determine the rates of VCLK and CLKVAL[9:0]. STN: VCLK = HCLK / (CLKVAL x 2) ( CLKVAL 2 ) TFT: VCLK = HCLK / [(CLKVAL+1) x 2] ( CLKVAL 0 ) Determine the toggle rate of the VM. 0 = Each Frame 1 = The rate defined by the MVAL Select the display mode. 00 = 4-bit dual scan display mode (STN) 01 = 4-bit single scan display mode (STN) 10 = 8-bit single scan display mode (STN) 11 = TFT LCD panel Select the BPP (Bits Per Pixel) mode. 0000 = 1 bpp for STN, Monochrome mode 0001 = 2 bpp for STN, 4-level gray mode 0010 = 4 bpp for STN, 16-level gray mode 0011 = 8 bpp for STN, color mode 0100 = 12 bpp for STN, color mode 1000 = 1 bpp for TFT 1001 = 2 bpp for TFT 1010 = 4 bpp for TFT 1011 = 8 bpp for TFT 1100 = 16 bpp for TFT 1101 = 24 bpp for TFT LCD video output and the logic enable/disable. 0 = Disable the video output and the LCD control signal. 1 = Enable the video output and the LCD control signal.
Initial State 0000000000 0000000000
MMODE PNRMODE
[7] [6:5]
0 00
BPPMODE
[4:1]
0000
ENVID
[0]
0
15-26
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
LCD CONTROLLER
LCD Control 2 Register Register LCDCON2 Address 0X4D000004 R/W R/W Description LCD control 2 register Reset Value 0x00000000
LCDCON2 VBPD
Bit [31:24]
Description TFT: Vertical back porch is the number of inactive lines at the start of a frame, after vertical synchronization period. STN: These bits should be set to zero on STN LCD. TFT/STN: These bits determine the vertical size of LCD panel. TFT: Vertical front porch is the number of inactive lines at the end of a frame, before vertical synchronization period. STN: These bits should be set to zero on STN LCD. TFT: Vertical sync pulse width determines the VSYNC pulse's high level width by counting the number of inactive lines. STN: These bits should be set to zero on STN LCD.
Initial State 0x00
LINEVAL VFPD
[23:14] [13:6]
0000000000 00000000
VSPW
[5:0]
000000
15-27
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
LCD CONTROLLER
S3C2440X RISC MICROPROCESSOR
LCD Control 3 Register Register LCDCON3 Address 0X4D000008 R/W R/W Description LCD control 3 register Reset Value 0x00000000
LCDCON3 HBPD (TFT) WDLY (STN)
Bit [25:19]
Description TFT: Horizontal back porch is the number of VCLK periods between the falling edge of HSYNC and the start of active data. STN: WDLY[1:0] bits determine the delay between VLINE and VCLK by counting the number of the HCLK. WDLY[7:2] are reserved. 00 = 16 HCLK, 01 = 32 HCLK, 10 = 48 HCLK, 11 = 64 HCLK
Initial state 0000000
HOZVAL
[18:8]
TFT/STN: These bits determine the horizontal size of LCD panel. HOZVAL has to be determined to meet the condition that total bytes of 1 line are 4n bytes. If the x size of LCD is 120 dot in mono mode, x=120 cannot be supported because 1 line consists of 15 bytes. Instead, x=128 in mono mode can be supported because 1 line is composed of 16 bytes (2n). LCD panel driver will discard the additional 8 dot.
00000000000
HFPD (TFT) LINEBLANK (STN)
[7:0]
TFT: Horizontal front porch is the number of VCLK periods between the end of active data and the rising edge of HSYNC. STN: These bits indicate the blank time in one horizontal line duration time. These bits adjust the rate of the VLINE finely. The unit of LINEBLANK is HCLK x 8. Ex) If the value of LINEBLANK is 10, the blank time is inserted to VCLK during 80 HCLK.
0X00
15-28
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
LCD CONTROLLER
LCD Control 4 Register Register LCDCON4 Address 0X4D00000C R/W R/W Description LCD control 4 register Reset Value 0x00000000
LCDCON4 MVAL HSPW(TFT) WLH(STN)
Bit [15:8] [7:0]
Description STN: These bit define the rate at which the VM signal will toggle if the MMODE bit is set to logic '1'. TFT: Horizontal sync pulse width determines the HSYNC pulse's high level width by counting the number of the VCLK. STN: WLH[1:0] bits determine the VLINE pulse's high level width by counting the number of the HCLK. WLH[7:2] are reserved. 00 = 16 HCLK, 01 = 32 HCLK, 10 = 48 HCLK, 11 = 64 HCLK
Initial state 0X00 0X00
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
LCD CONTROLLER
S3C2440X RISC MICROPROCESSOR
LCD Control 5 Register Register LCDCON5 Address 0X4D000010 R/W R/W Description LCD control 5 register Reset Value 0x00000000
LCDCON5 Reserved VSTATUS
Bit [31:17] [16:15]
Description This bit is reserved and the value should be `0'. TFT: Vertical Status (read only). 00 = VSYNC 01 = BACK Porch 10 = ACTIVE 11 = FRONT Porch TFT: Horizontal Status (read only). 00 = HSYNC 01 = BACK Porch 10 = ACTIVE 11 = FRONT Porch TFT: This bit determines the order of 24 bpp video memory. 0 = LSB valid 1 = MSB Valid TFT: This bit selects the format of 16 bpp output video data. 0 = 5:5:5:1 Format 1 = 5:6:5 Format STN/TFT: This bit controls the polarity of the VCLK active edge. 0 = The video data is fetched at VCLK falling edge 1 = The video data is fetched at VCLK rising edge STN/TFT: This bit indicates the VLINE/HSYNC pulse polarity. 0 = Normal 1 = Inverted STN/TFT: This bit indicates the VFRAME/VSYNC pulse polarity. 0 = Normal 1 = Inverted STN/TFT: This bit indicates the VD (video data) pulse polarity. 0 = Normal 1 = VD is inverted.
Initial state 0 00
HSTATUS
[14:13]
00
BPP24BL
[12]
0
FRM565
[11]
0
INVVCLK
[10]
0
INVVLINE INVVFRAME
[9] [8]
0 0
INVVD
[7]
0
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
LCD CONTROLLER
LCD Control 5 Register (Continued) LCDCON5 INVVDEN INVPWREN INVLEND PWREN ENLEND BSWP HWSWP Bit [6] [5] [4] [3] [2] [1] [0] Description TFT: This bit indicates the VDEN signal polarity. 0 = normal 1 = inverted STN/TFT: This bit indicates the PWREN signal polarity. 0 = normal 1 = inverted TFT: This bit indicates the LEND signal polarity. 0 = normal 1 = inverted STN/TFT: LCD_PWREN output signal enable/disable. 0 = Disable PWREN signal 1 = Enable PWREN signal TFT: LEND output signal enable/disable. 0 = Disable LEND signal 1 = Enable LEND signal STN/TFT: Byte swap control bit. 0 = Swap Disable 1 = Swap Enable STN/TFT: Half-Word swap control bit. 0 = Swap Disable 1 = Swap Enable Initial state 0 0 0 0 0 0 0
15-31
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
LCD CONTROLLER
S3C2440X RISC MICROPROCESSOR
FRAME BUFFER START ADDRESS 1 REGISTER Register LCDSADDR1 Address 0X4D000014 R/W R/W Description STN/TFT: Frame buffer start address 1 register Reset Value 0x00000000
LCDSADDR1 LCDBANK
Bit [29:21]
Description These bits indicate A[30:22] of the bank location for the video buffer in the system memory. LCDBANK value cannot be changed even when moving the view port. LCD frame buffer should be within aligned 4MB region, which ensures that LCDBANK value will not be changed when moving the view port. So, care should be taken to use the malloc() function. For dual-scan LCD : These bits indicate A[21:1] of the start address of the upper address counter, which is for the upper frame memory of dual scan LCD or the frame memory of single scan LCD. For single-scan LCD : These bits indicate A[21:1] of the start address of the LCD frame buffer.
Initial State 0x00
LCDBASEU
[20:0]
0x000000
FRAME Buffer Start Address 2 Register Register LCDSADDR2 Address 0X4D000018 R/W R/W Description STN/TFT: Frame buffer start address 2 register Reset Value 0x00000000
LCDSADDR2 LCDBASEL
Bit [20:0]
Description For dual-scan LCD: These bits indicate A[21:1] of the start address of the lower address counter, which is used for the lower frame memory of dual scan LCD. For single scan LCD: These bits indicate A[21:1] of the end address of the LCD frame buffer. LCDBASEL = ((the frame end address) >>1) + 1 = LCDBASEU + (PAGEWIDTH+OFFSIZE) x (LINEVAL+1)
Initial State 0x0000
Note:
Users can change the LCDBASEU and LCDBASEL values for scrolling while the LCD controller is turned on. But, users must not change the value of the LCDBASEU and LCDBASEL registers at the end of FRAME by referring to the LINECNT field in LCDCON1 register, for the LCD FIFO fetches the next frame data prior to the change in the frame. So, if you change the frame, the pre-fetched FIFO data will be obsolete and LCD controller will display an incorrect screen. To check the LINECNT, interrupts should be masked. If any interrupt is executed just after reading LINECNT, the read LINECNT value may be obsolete because of the execution time of Interrupt Service Routine (ISR).
15-32
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
LCD CONTROLLER
FRAME Buffer Start Address 3 Register Register LCDSADDR3 Address 0X4D00001C R/W R/W Description STN/TFT: Virtual screen address set Reset Value 0x00000000
LCDSADDR3 OFFSIZE
Bit [21:11]
Description Virtual screen offset size (the number of half words). This value defines the difference between the address of the last half word displayed on the previous LCD line and the address of the first half word to be displayed in the new LCD line. Virtual screen page width (the number of half words). This value defines the width of the view port in the frame.
Initial State 00000000000
PAGEWIDTH
Note:
[10:0]
000000000
The values of PAGEWIDTH and OFFSIZE must be changed when ENVID bit is 0.
Example 1. LCD panel = 320 x 240, 16gray, single scan Frame start address = 0x0c500000 Offset dot number = 2048 dots ( 512 half words ) LINEVAL = 240-1 = 0xef PAGEWIDTH = 320 x 4 / 16 = 0x50 OFFSIZE = 512 = 0x200 LCDBANK = 0x0c500000 >> 22 = 0x31 LCDBASEU = 0x100000 >> 1 = 0x80000 LCDBASEL = 0x80000 + ( 0x50 + 0x200 ) x ( 0xef + 1 ) = 0xa2b00 Example 2. LCD panel = 320 x 240, 16gray, dual scan Frame start address = 0x0c500000 Offset dot number = 2048 dots ( 512 half words ) LINEVAL = 120-1 = 0x77 PAGEWIDTH = 320 x 4 / 16 = 0x50 OFFSIZE = 512 = 0x200 LCDBANK = 0x0c500000 >> 22 = 0x31 LCDBASEU = 0x100000 >> 1 = 0x80000 LCDBASEL = 0x80000 + ( 0x50 + 0x200 ) x ( 0x77 + 1 ) = 0x91580 Example 3. LCD panel = 320*240, color, single scan Frame start address = 0x0c500000 Offset dot number = 1024 dots ( 512 half words ) LINEVAL = 240-1 = 0xef PAGEWIDTH = 320 x 8 / 16 = 0xa0 OFFSIZE = 512 = 0x200 LCDBANK = 0x0c500000 >> 22 = 0x31 LCDBASEU = 0x100000 >> 1 = 0x80000 LCDBASEL = 0x80000 + ( 0xa0 + 0x200 ) x ( 0xef + 1 ) = 0xa7600
15-33
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
LCD CONTROLLER
S3C2440X RISC MICROPROCESSOR
RED Lookup Table Register Register REDLUT Address 0X4D000020 R/W R/W Description STN: Red lookup table register Reset Value 0x00000000
REDLUT REDVAL
Bit [31:0]
Description These bits define which of the 16 shades will be chosen by each of the 8 possible red combinations. 000 = REDVAL[3:0], 010 = REDVAL[11:8], 100 = REDVAL[19:16], 110 = REDVAL[27:24], 001 = REDVAL[7:4] 011 = REDVAL[15:12] 101 = REDVAL[23:20] 111 = REDVAL[31:28]
Initial State 0x00000000
GREEN Lookup Table Register Register GREENLUT Address 0X4D000024 R/W R/W Description STN: Green lookup table register Reset Value 0x00000000
GREENLUT GREENVAL
Bit [31:0]
Description These bits define which of the 16 shades will be chosen by each of the 8 possible green combinations. 000 = GREENVAL[3:0], 010 = GREENVAL[11:8], 100 = GREENVAL[19:16], 110 = GREENVAL[27:24], 001 = GREENVAL[7:4] 011 = GREENVAL[15:12] 101 = GREENVAL[23:20] 111 = GREENVAL[31:28]
Initial State 0x00000000
BLUE Lookup Table Register Register BLUELUT Address 0X4D000028 R/W R/W Description STN: Blue lookup table register Reset Value 0x0000
BULELUT BLUEVAL
Bit [15:0]
Description These bits define which of the 16 shades will be chosen by each of the 4 possible blue combinations. 00 = BLUEVAL[3:0], 10 = BLUEVAL[11:8], 01 = BLUEVAL[7:4] 11 = BLUEVAL[15:12]
Initial State 0x0000
Note:
Address from 0x14A0002C to 0x14A00048 should not be used. This area is reserved for Test mode.
15-34
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
LCD CONTROLLER
Dithering Mode Register Register DITHMODE Address 0X4D00004C R/W R/W Description STN: Dithering mode register. This register reset value is 0x00000 But, user can change this value to 0x12210. (Refer to a sample program source for the latest value of this register.) Reset Value 0x00000
DITHMODE DITHMODE
Bit [18:0] 0x00000 or 0x12210
Description Use one of following value for your LCD :
Initial state 0x00000
15-35
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
LCD CONTROLLER
S3C2440X RISC MICROPROCESSOR
Temp Palette Register Register TPAL Address 0X4D000050 R/W R/W Description TFT: Temporary palette register. This register value will be video data at next frame. Reset Value 0x00000000
TPAL TPALEN TPALVAL
Bit [24] [23:0] 0 = Disable TPALVAL[23:16] : RED TPALVAL[15:8] : GREEN TPALVAL[7:0] : BLUE
Description Temporary palette register enable bit. 1 = Enable Temporary palette value register.
Initial state 0 0x000000
15-36
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
LCD CONTROLLER
LCD Interrupt Pending Register Register LCDINTPND Address 0X4D000054 R/W R/W Description Indicate the LCD interrupt pending register Reset Value 0x0
LCDINTPND INT_FrSyn
Bit [1]
Description LCD frame synchronized interrupt pending bit. 0 = The interrupt has not been requested. 1 = The frame has asserted the interrupt request.
Initial state 0
INT_FiCnt
[0]
LCD FIFO interrupt pending bit. 0 = The interrupt has not been requested. 1 = LCD FIFO interrupt is requested when LCD FIFO reaches trigger level.
0
LCD Source Pending Register Register LCDSRCPND Address 0X4D000058 R/W R/W Description Indicate the LCD interrupt source pending register Reset Value 0x0
LCDSRCPND INT_FrSyn
Bit [1]
Description LCD frame synchronized interrupt source pending bit. 0 = The interrupt has not been requested. 1 = The frame has asserted the interrupt request.
Initial state 0
INT_FiCnt
[0]
LCD FIFO interrupt source pending bit. 0 = The interrupt has not been requested. 1 = LCD FIFO interrupt is requested when LCD FIFO reaches trigger level.
0
15-37
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
LCD CONTROLLER
S3C2440X RISC MICROPROCESSOR
LCD Interrupt Mask Register Register LCDINTMSK Address 0X4D00005C R/W R/W Description Determine which interrupt source is masked. The masked interrupt source will not be serviced. Reset Value 0x3
LCDINTMSK FIWSEL INT_FrSyn
Bit [2] [1] 0 = 4 words
Description Determine the trigger level of LCD FIFO. 1 = 8 words Mask LCD frame synchronized interrupt. 0 = The interrupt service is available. 1 = The interrupt service is masked.
Initial state
1
INT_FiCnt
[0]
Mask LCD FIFO interrupt. 0 = The interrupt service is available. 1 = The interrupt service is masked.
1
15-38
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
LCD CONTROLLER
TCON Control Register Register TCONSEL Address 0X4D000060 R/W R/W Description This register controls the LPC3600/LCC3600 modes. Reset Value 0xF84
TCONSEL LCC_TEST2 LCC_TEST1 LCC_SEL5 LCC_SEL4 LCC_SEL3 LCC_SEL2 LCC_SEL1 LCC_EN
Bit [11] [10] [9] [8] [7] [6] [5] [4]
Description LCC3600 Test Mode 2 ( Read Only ) LCC3600 Test Mode 1 ( Read Only ) Select STV polarity Select CPV signal pin 0 Select CPV signal pin 1 Select Line/Dot inversion Select DG/Normal mode Determine LCC3600 Enable/Disable 0 = LCC3600 Disable 1 = LCC3600 Enable
Initial state 1 1 1 1 1 0 0 0 0 1
CPV_SEL MODE_SEL
[3] [2]
Select CPV Pulse low width Select DE/Sync mode 0 = Sync mode 1 = DE mode
RES_SEL
[1]
Select output resolution type 0 = 320 x 240 1 = 240 x 320 Determine LPC3600 Enable/Disable 0
LPC_EN
[0]
0 = LPC3600 Disable 1 = LPC3600 Enable
0
Note : Both LPC_EN and LCC_EN enable is not permitted. Only one TCON can be enabled at the same time.
15-39
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
LCD CONTROLLER
S3C2440X RISC MICROPROCESSOR
Register Setting Guide (STN) The LCD controller supports multiple screen sizes by special register setting. The CLKVAL value determines the frequency of VCLK. This value has to be determined such that the VCLK value is greater than data transmission rate. The data transmission rate for the VD port of the LCD controller is used to determine the value of CLKVAL register. The data transmission rate is given by the following equation:
Data transmission rate = HS x VS x FR x MV HS: Horizontal LCD size VS: Vertical LCD size FR: Frame rate MV: Mode dependent value Table 15-6. MV Value for Each Display Mode Mode Mono, 4-bit single scan display Mono, 8-bit single scan display or 4-bit dual scan display 4 level gray, 4-bit single scan display 4 level gray, 8-bit single scan display or 4-bit dual scan display 16 level gray, 4-bit single scan display 16 level gray, 8-bit single scan display or 4-bit dual scan display Color, 4-bit single scan display Color, 8-bit single scan display or 4-bit dual scan display MV Value 1/4 1/8 1/4 1/8 1/4 1/8 3/4 3/8
The LCDBASEU register value is the first address value of the frame buffer. The lowest 4 bits must be eliminated for burst 4 word access. The LCDBASEL register value depends on LCD size and LCDBASEU. The LCDBASEL value is given by the following equation: LCDBASEL = LCDBASEU + LCDBASEL offset
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
LCD CONTROLLER
Example 1: 160 x 160, 4-level gray, 80 frame/sec, 4-bit single scan display, HCLK frequency is 60 MHz WLH = 1, WDLY = 1. Data transmission rate = 160 x 160 x 80 x 1/4 = 512 kHz CLKVAL = 58, VCLK = 517KHz HOZVAL = 39, LINEVAL = 159 LINEBLANK =10 LCDBASEL = LCDBASEU + 3200
Note: The higher the system load is, the lower the cpu performance is.
Example 2 (Virtual screen register): 4 -level gray, Virtual screen size = 1024 x 1024, LCD size = 320 x 240, LCDBASEU = 0x64, 4-bit dual scan. 1 halfword = 8 pixels (4-level gray), Virtual screen 1 line = 128 halfword = 1024 pixels, LCD 1 line = 320 pixels = 40 halfword, OFFSIZE = 128 - 40 = 88 = 0x58, PAGEWIDTH = 40 = 0x28 LCDBASEL = LCDBASEU + (PAGEWIDTH + OFFSIZE) x (LINEVAL +1) = 100 + (40 +88) x 120 = 0x3C64
15-41
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
LCD CONTROLLER
S3C2440X RISC MICROPROCESSOR
Gray Level Selection Guide The S3C2440X LCD controller can generate 16 gray level using Frame Rate Control (FRC). The FRC characteristics may cause unexpected patterns in gray level. These unwanted erroneous patterns may be shown in fast response LCD or at lower frame rates. Because the quality of LCD gray levels depends on LCD's own characteristics, the user has to select an appropriate gray level after viewing all gray levels on user's own LCD.
Select the gray level quality through the following procedures: 1. Get the latest dithering pattern register value from SAMSUNG. 2. Display 16 gray bar in LCD. 3. Change the frame rate into an optimal value. 4. Change the VM alternating period to get the best quality. 5. As viewing 16 gray bars, select a good gray level, which is displayed well on your LCD. 6. Use only the good gray levels for quality.
LCD Refresh Bus Bandwidth Calculation Guide The S3C2440X LCD controller can support various LCD display sizes. To select a suitable size (for the flicker free LCD system application), the user have to consider the LCD refresh bus bandwidth determined by the LCD display size, bit per pixel (bpp), frame rate, memory bus width, memory type, and so on. LCD Data Rate (Byte/s) = bpp x (Horizontal display size) x (Vertical display size) x (Frame rate) /8 LCD DMA Burst Count (Times/s) = LCD Data Rate(Byte/s) /16(Byte) ; LCD DMA using 4words(16Byte) burst Pdma means LCD DMA access period. In other words, the value of Pdma indicates the period of four-beat burst (4-words burst) for video data fetch. So, Pdma depends on memory type and memory setting. Eventually, LCD System Load is determined by LCD DMA Burst Count and Pdma. LCD System Load = LCD DMA Burst Count x Pdma
Example 3: 640 x 480, 8bpp, 60 frame/sec, 16-bit data bus width, SDRAM (Trp=2HCLK / Trcd=2HCLK / CL=2HCLK) and HCLK frequency is 60 MHz LCD Data Rate = 8 x 640 x 480 x 60 / 8 = 18.432Mbyte/s LCD DMA Burst Count = 18.432 / 16 = 1.152M/s Pdma = (Trp+Trcd+CL+(2 x 4)+1) x (1/60MHz) = 0.250ms LCD System Load = 1.152 x 250 = 0.288 System Bus Occupation Rate = (0.288/1) x 100 = 28.8%
15-42
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
LCD CONTROLLER
Register Setting Guide (TFT LCD) The CLKVAL register value determines the frequency of VCLK and frame rate. Frame Rate = 1/ [ { (VSPW+1) + (VBPD+1) + (LIINEVAL + 1) + (VFPD+1) } x {(HSPW+1) + (HBPD +1) + (HFPD+1) + (HOZVAL + 1) } x { 2 x ( CLKVAL+1 ) / ( HCLK ) } ] For applications, the system timing must be considered to avoid under-run condition of the fifo of the lcd controller caused by memory bandwidth contention. Example 4: TFT Resolution: 240 x 240, VSPW =2, VBPD =14, LINEVAL = 239, VFPD =4 HSPW =25, HBPD =15, HOZVAL = 239, HFPD =1 CLKVAL = 5 HCLK = 60 M (hz) The parameters below must be referenced by LCD size and driver specifications: VSPW, VBPD, LINEVAL, VFPD, HSPW, HBPD, HOZVAL, and HFPD If target frame rate is 60-70Hz, then CLKVAL should be 5. So, Frame Rate = 67Hz
15-43
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
LCD CONTROLLER
S3C2440X RISC MICROPROCESSOR
NOTES
15-44
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
ADC AND TOUCH SCREEN INTERFACE
16ADC&TOUCHSCREENI
OVERVIEW
FEATURES -- Resolution: 10-bit -- Differential Linearity Error: -- Integral Linearity Error: 1.0 LSB 2.0 LSB
NTERFACE
The 10-bit CMOS ADC(Analog to Digital Converter) is a recycling type device with 8-channel analog inputs. It converts the analog input signal into 10-bit binary digital codes at a maximum conversion rate of 500KSPS with 2.5MHz A/D converter clock. A/D converter operates with on-chip sample-and-hold function and power down mode is supported. Touch Screen Interface is controlling and selecting pads(XP, XM, YP, YM) of the Touch Screen for X, Y position conversion. The Touch Screen Interface contains Touch Screen Pads control logic and ADC interface logic with an interrupt generation logic.
-- Maximum Conversion Rate: 500 KSPS -- Low Power Consumption -- Power Supply Voltage: 3.3V -- Analog Input Range: 0 ~ 3.3V -- On-chip sample-and-hold function -- Normal Conversion Mode -- Separate X/Y position conversion Mode -- Auto(Sequential) X/Y Position Conversion Mode -- Waiting for Interrupt Mode
7-1
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
ADC AND TOUCH SCREEN INTERFACE
S3C2440X RISC MICROPROCESSOR
ADC & TOUCH SCREEN INTERFACE OPERATION
BLOCK DIAGRAM Figure 16-1 shows the functional block diagram of A/D converter and Touch Screen Interface. Note that the A/D converter device is a recycling type.
A VDD AGND Pullup XP XM note Touch Screen Pads control
8:1
YP YM note
ADC interface A/D &Touch Screen Converter Control
MUX
A[3:0] ADC input control Waiting for Interrupt Mode
INT_ADC Interrupt Generation INT_WKU
Figure 16-1. ADC and Touch Screen Interface Functional Block Diagram *note (symbol ) When Touch Screen device is used, XM or PM is only connected ground for Touch Screen I/F. When Touch Screen device is not used, XM or PM is connecting Analog Input Signal for Normal ADC conversion.
7-2
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
ADC AND TOUCH SCREEN INTERFACE
FUNCTION DESCRIPTIONS
A/D Conversion Time When the GCLK frequency is 50MHz and the prescaler value is 49, total 10-bit conversion time is as follows. A/D converter freq. = 50MHz/(49+1) = 1MHz Conversion time = 1/(1MHz / 5cycles) = 1/200KHz = 5 us
NOTE: This A/D converter was designed to operate at maximum 2.5MHz clock, so the conversion rate can go up to 500 KSPS.
Touch Screen Interface Mode 1. Normal Conversion Mode Single Conversion Mode is the most likely used for General Purpose ADC Conversion. This mode can be initialized by setting the ADCCON (ADC Control Register) and completed with a read and a write to the ADCDAT0 (ADC Data Register 0). 2. Separate X/Y position conversion Mode Touch Screen Controller can be operated by one of two Conversion Modes. Separate X/Y Position Conversion Mode is operated as the following way. X-Position Mode writes X-Position Conversion Data to ADCDAT0, so Touch Screen Interface generates the Interrupt source to Interrupt Controller. Y-Position Mode writes Y-Position Conversion Data to ADCDAT1, so Touch Screen Interface generates the Interrupt source to Interrupt Controller. 3. Auto(Sequential) X/Y Position Conversion Mode Auto(Sequential) X/Y Position Conversion Mode is operated as the following. Touch Screen Controller sequentially converts X-Position and Y-Position that is touched. After Touch controller writes X-measurement data to ADCDAT0 and writes Y-measurement data to ADCDAT1, Touch Screen Interface is generating Interrupt source to Interrupt Controller in Auto Position Conversion Mode. 4. Waiting for Interrupt Mode Touch Screen Controller is generating wake-up (WKU) signal when the system is STOP mode (Power Down). The Waiting for Interrupt Mode of Touch Screen Controller must be set state of Pads(XP, XM, YP, YM) in Touch Screen Interface. After Touch Screen Controller is generating Wake-Up signal (INT_WKU), Waiting for interrupt Mode must be cleared. (XY_PST sets to the No operation Mode)
Standby Mode Standby mode is activated when ADCCON [2] is set to '1'. In this mode, A/D conversion operation is halted and ADCDAT0, ADCDAT1 register contains the previous converted data.
7-3
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
ADC AND TOUCH SCREEN INTERFACE
S3C2440X RISC MICROPROCESSOR
Programming Notes 1. The A/D converted data can be accessed by means of interrupt or polling method. With interrupt method the overall conversion time - from A/D converter start to converted data read - may be delayed because of the return time of interrupt service routine and data access time. With polling method, by checking the ADCCON[15] - end of conversion flag-bit, the read time from ADCDAT register can be determined. Another way for starting A/D conversion is provided. After ADCCON[1] - A/D conversion start-by-read mode-is set to 1, A/D conversion starts simultaneously whenever converted data is read.
2.
X-Conversion
Y-Conversion
XP
Pen Touch
YP
X-Tal CLK is used GCLK is used
Figure 16-2 ADC and Touch Screen Operation signal
7-4
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
ADC AND TOUCH SCREEN INTERFACE
ADC AND TOUCH SCREEN INTERFACE SPECIAL REGISTERS
ADC CONTROL REGISTER (ADCCON) Register ADCCON Address 0x5800000 R/W R/W Description ADC Control Register Reset Value 0x3FC4
ADCCON ECFLG
Bit [15]
Description End of conversion flag(Read only) 0 = A/D conversion in process 1 = End of A/D conversion A/D converter prescaler enable 0 = Disable 1 = Enable
Initial State 0
PRSCEN
[14]
0
PRSCVL
[13:6]
A/D converter prescaler value Data value: 0 ~ 255 Note that division factor is (N+1) when prescaler value is N. Analog input channel select 000 = AIN 0 001 = AIN 1 010 = AIN 2 011 = AIN 3 100 = YM 101 = YP 110 = XM 111 = XP Standby mode select 0 = Normal operation mode 1 = Standby mode A/D conversion start by read 0 = Disable start by read operation 1 = Enable start by read operation A/D conversion starts by enable. If READ_START is enabled, this value is not valid. 0 = No operation 1 = A/D conversion starts and this bit is cleared after the start-up.
0xFF
SEL_MUX
[5:3]
0
STDBM
[2]
1
READ_ START
[1]
0
ENABLE_START
[0]
0
NOTE : When Touch Screen Pads(YM, YP, XM, XP) were disabled, these ports can be used as Analog input ports(AIN4, AIN5, AIN6, AIN7) for ADC.
7-5
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
ADC AND TOUCH SCREEN INTERFACE
S3C2440X RISC MICROPROCESSOR
ADC TOUCH SCREEN CONTROL REGISTER (ADCTSC) Register ADCTSC Address 0x5800004 R/W R/W Description ADC Touch Screen Control Register Reset Value 0x58
ADCTSC UD_SEN
Bit [8]
Description Detect Stylus Up or Down status. 0 = Detect Stylus Down Interrupt Signal. 1 = Detect Stylus Up Interrupt Signal. YM Switch Enable 0 = YM Output Driver Disable. 1 = YM Output Driver Enable. YP Switch Enable 0 = YP Output Driver Enable. 1 = YP Output Driver Disable. XM Switch Enable 0 = XM Output Driver Disable. 1 = XM Output Driver Enable. XP Switch Enable 0 = XP Output Driver Enable. 1 = XP Output Driver Disable. Pull-up Switch Enable 0 = XP Pull-up Enable. 1 = XP Pull-up Disable. Automatically sequencing conversion of X-Position and Y-Position 0 = Normal ADC conversion. 1 = Auto Sequential measurement of X-position, Y-position. Manually measurement of X-Position or Y-Position.
Initial State 0
YM_SEN
[7]
0
YP_SEN
[6]
1
XM_SEN
[5]
0
XP_SEN
[4]
1
PULL_UP
[3]
1
AUTO_PST
[2]
0
XY_PST
[1:0]
0
00 = No operation mode 01 = X-position measurement 10 = Y-position measurement 11 = Waiting for Interrupt Mode NOTE: 1) While waiting for Touch screen Interrupt, XP_SEN bit should be set to `1', namely `XP Output disable' and PULL_UP bit should be set to `0', namely `XP Pull-up enable'. 2) AUTO_PST bit should be set `1' only in Automatic & Sequential X/Y Position conversion. Touch screen pin conditions in X/Y position conversion. XP X Position Y Position Vref Hi-Z XM GND Hi-Z YP Hi-Z Vref YM Hi-Z GND ADC ch. select YP XP
7-6
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
ADC AND TOUCH SCREEN INTERFACE
ADC START DELAY REGISTER (ADCDLY) Register ADCDLY Address 0x5800008 R/W R/W Description ADC Start or Interval Delay Register Reset Value 0x00ff
ADCDLY DELAY
Bit [15:0]
Description 1) Normal Conversion Mode, XY Position Mode, Auto Position Mode. ADC conversion start delay value. 2) Waiting for Interrupt Mode. When Stylus Down occurs at SLEEP MODE, generates Wake-Up signal, having interval(several ms), for Exiting SLEEP MODE. Note) Don't use Zero value(0x0000)
Initial State 00ff
NOTE: Before ADC conversion, Touch screen uses X-tal clock(3.68MHz). During ADC conversion GCLK( Max. 50MHz) is used.
7-7
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
ADC AND TOUCH SCREEN INTERFACE
S3C2440X RISC MICROPROCESSOR
ADC CONVERSION DATA REGISTER (ADCDAT0) Register ADCDAT0 Address 0x580000C R/W R Description ADC Conversion Data Register Reset Value -
ADCDAT0 UPDOWN
Bit [15]
Description Up or Down state of Stylus at Waiting for Interrupt Mode. 0 = Stylus down state. 1 = Stylus up state. Automatic sequencing conversion of X-Position and Y-Position 0 = Normal ADC conversion. 1 = Sequencing measurement of X-position, Y-position. Manually measurement of X-Position or Y-Position. 00 = No operation mode 01 = X-position measurement 10 = Y-position measurement 11 = Waiting for Interrupt Mode
Initial State -
AUTO_PST
[14]
-
XY_PST
[13:12]
-
Reserved XPDATA (Normal ADC)
[11:10] [9:0]
Reserved X-Position Conversion data value (include Normal ADC Conversion data value) Data value : 0 ~ 3FF -
7-8
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
ADC AND TOUCH SCREEN INTERFACE
ADC CONVERSION DATA REGISTER (ADCDAT1) Register ADCDAT1 Address 0x5800010 R/W R Description ADC Conversion Data Register Reset Value -
ADCDAT1 UPDOWN
Bit [15]
Description Up or Down state of Stylus at Waiting for Interrupt Mode. 0 = Stylus down state. 1 = No stylus down state. Automatically sequencing conversion of X-Position and Y-Position 0 = Normal ADC conversion. 1 = Sequencing measurement of X-position, Y-position. Manually measurement of X-Position or Y-Position. 00 = No operation mode 01 = X-position measurement 10 = Y-position measurement 11 = Waiting for Interrupt Mode
Initial State -
AUTO_PST
[14]
-
XY_PST
[13:12]
-
Reserved YPDATA
[11:10] [9:0]
Reserved Y-Position Conversion data value Data value : 0 ~ 3FF -
7-9
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
ADC AND TOUCH SCREEN INTERFACE
S3C2440X RISC MICROPROCESSOR
ADC TOUCH SCREEN UP-DOWN REGISTER (ADCUPDN) Register ADCUPDN Address 0x5800014 R/W R/W Description Stylus Up or Down Interrpt status register Reset Value 0x0
ADCUPDN TSC_UP
Bit [1]
Description Stylus Up Interrupt. 0 = No stylus up status. 1 = Stylus up status. Stylus Down Interrupt. 0 = No stylus down status. 1 = Stylus down status.
Initial State 0
TSC_DN
[0]
0
7-10
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
REAL TIME CLOCK
17
OVERVIEW
FEATURES
REAL TIME CLOCK
The Real Time Clock (RTC) unit can be operated by the backup battery while the system power is off. The RTC can transmit 8-bit data to CPU as Binary Coded Decimal (BCD) values using the STRB/LDRB ARM operation. The data include the time by second, minute, hour, date, day, month, and year. The RTC unit works with an external 32.768 KHz crystal and also can perform the alarm function.
-- BCD number: second, minute, hour, date, day, month, and year -- Leap year generator -- Alarm function: alarm interrupt or wake-up from power-off mode -- Year 2000 problem is removed. -- Independent power pin (RTCVDD) -- Supports millisecond tick time interrupt for RTOS kernel time tick. -- Round reset function
17-1
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
REAL TIME CLOCK
S3C2440X RISC MICROPROCESSOR
REAL TIME CLOCK OPERATION
TICNT
Time Tick Generator
128 Hz RTCRST
TIME TICK
215 Clock Divider
XTIrtc 1 Hz
Reset Register
Leap Year Generator
SEC
XTOrtc
MIN
HOUR
DAY
DATE
MON
YEAR
Control Register
RTCCON
Alarm Generator
RTCALM
PMWKUP
PWDN
ALMINT
Figure 17-1. Real Time Clock Block Diagram LEAP YEAR GENERATOR The leap year generator can determine the last date of each month out of 28, 29, 30, or 31, based on data from BCDDATE, BCDMON, and BCDYEAR. This block considers leap year in deciding on the last date. An 8-bit counter can only represent 2 BCD digits, so it cannot decide whether "00" year (the year with its last two digits zeros) is a leap year or not. For example, it cannot discriminate between 1900 and 2000. To solve this problem, the RTC block in S3C2440X has hard-wired logic to support the leap year in 2000. Note 1900 is not leap year while 2000 is leap year. Therefore, two digits of 00 in S3C2440X denote 2000, not 1900. READ/WRITE REGISTERS Bit 0 of the RTCCON register must be set high in order to write the BCD register in RTC block. To display the second, minute, hour, date, month, and year, the CPU should read the data in BCDSEC, BCDMIN, BCDHOUR, BCDDAY, BCDDATE, BCDMON, and BCDYEAR registers, respectively, in the RTC block. However, a one second deviation may exist because multiple registers are read. For example, when the user reads the registers from BCDYEAR to BCDMIN, the result is assumed to be 2059 (Year), 12 (Month), 31 (Date), 23 (Hour) and 59 (Minute). When the user read the BCDSEC register and the value ranges from 1 to 59 (Second), there is no problem, but, if the value is 0 sec., the year, month, date, hour, and minute may be changed to 2060 (Year), 1 (Month), 1 (Date), 0 (Hour) and 0 (Minute) because of the one second deviation that was mentioned. In this case, the user should reread from BCDYEAR to BCDSEC if BCDSEC is zero. BACKUP BATTERY OPERATION The RTC logic can be driven by the backup battery, which supplies the power through the RTCVDD pin into the RTC block, even if the system power is off. When the system is off, the interfaces of the CPU and RTC logic should be blocked, and the backup battery only drives the oscillation circuit and the BCD counters to minimize power dissipation.
17-2
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
REAL TIME CLOCK
ALARM FUNCTION The RTC generates an alarm signal at a specified time in the power-off mode or normal operation mode. In normal operation mode, the alarm interrupt (ALMINT) is activated. In the power-off mode, the power management wakeup (PMWKUP) signal is activated as well as the ALMINT. The RTC alarm register (RTCALM) determines the alarm enable/disable status and the condition of the alarm time setting. TICK TIME INTERRUPT The RTC tick time is used for interrupt request. The TICNT register has an interrupt enable bit and the count value for the interrupt. The count value reaches '0' when the tick time interrupt occurs. Then the period of interrupt is as follows: Period = ( n+1 ) / 128 second n: Tick time count value (1~127) This RTC time tick may be used for real time operating system (RTOS) kernel time tick. If time tick is generated by the RTC time tick, the time related function of RTOS will always synchronized in real time. ROUND RESET FUNCTION The round reset function can be performed by the RTC round reset register (RTCRST). The round boundary (30, 40, or 50 sec.) of the second carry generation can be selected, and the second value is rounded to zero in the round reset. For example, when the current time is 23:37:47 and the round boundary is selected to 40 sec, the round reset changes the current time to 23:38:00. NOTE All RTC registers have to be accessed for each byte unit using the STRB and LDRB instructions or char type pointer.
32.768KHZ X-TAL CONNECTION EXAMPLE The Figure 17-2 shows a circuit of the RTC unit oscillation at 32.768Khz.
15~ 22pF XTIrtc 32768Hz XTOrtc
Figure 17-2. Main Oscillator Circuit Example
17-3
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
REAL TIME CLOCK
S3C2440X RISC MICROPROCESSOR
REAL TIME CLOCK SPECIAL REGISTERS
REAL TIME CLOCK CONTROL (RTCCON) REGISTER The RTCCON register consists of 4 bits such as the RTCEN, which controls the read/write enable of the BCD registers, CLKSEL, CNTSEL, and CLKRST for testing. RTCEN bit can control all interfaces between the CPU and the RTC, so it should be set to 1 in an RTC control routine to enable data read/write after a system reset. Also before power off, the RTCEN bit should be cleared to 0 to prevent inadvertent writing into RTC registers. Register RTCCON Address 0x57000040(L) 0x57000043(B) R/W R/W (by byte) Description RTC control register Reset Value 0x0
RTCCON CLKRST CNTSEL
Bit [3] [2] RTC clock count reset. 0 = No reset, 1 = Reset
Description
Initial State 0 0
BCD count select. 0 = Merge BCD counters 1 = Reserved (Separate BCD counters) BCD clock select. 15 0 = XTAL 1/2 divided clock 1 = Reserved (XTAL clock only for test) RTC control enable. 0 = Disable 1 = Enable Note: Only BCD time count and read operation can be performed.
CLKSEL
[1]
0
RTCEN
[0]
0
Notes: 1. All RTC registers have to be accessed for each byte unit using STRB and LDRB instructions or char type pointer. 2. (L): Little endian. (B): Big endian.
TICK TIME COUNT (TICNT) REGISTER Register TICNT Address 0x57000044(L) 0x57000047(B) R/W R/W (by byte) Description Tick time count register Reset Value 0x0
TICNT TICK INT ENABLE TICK TIME COUNT
Bit [7] [6:0]
Description Tick time interrupt enable. 0 = Disable 1 = Enable Tick time count value (1~127). This counter value decreases internally, and users cannot read this counter value in working.
Initial State 0 000000
17-4
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
REAL TIME CLOCK
RTC ALARM CONTROL (RTCALM) REGISTER The RTCALM register determines the alarm enable and the alarm time. Note that the RTCALM register generates the alarm signal through both ALMINT and PMWKUP in power down mode, but only through ALMINT in the normal operation mode. Register RTCALM Address 0x57000050(L) 0x57000053(B) R/W R/W (by byte) Description RTC alarm control register Reset Value 0x0
RTCALM Reserved ALMEN YEAREN MONREN DATEEN HOUREN MINEN SECEN
Bit [7] [6] [5] [4] [3] [2] [1] [0]
Description Alarm global enable. 0 = Disable, 1 = Enable Year alarm enable. 0 = Disable, 1 = Enable Month alarm enable. 0 = Disable, 1 = Enable Date alarm enable. 0 = Disable, 1 = Enable Hour alarm enable. 0 = Disable, 1 = Enable Minute alarm enable. 0 = Disable, 1 = Enable Second alarm enable. 0 = Disable, 1 = Enable
Initial State 0 0 0 0 0 0 0 0
17-5
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
REAL TIME CLOCK
S3C2440X RISC MICROPROCESSOR
ALARM SECOND DATA (ALMSEC) REGISTER Register ALMSEC Address 0x57000054(L) 0x57000057(B) R/W R/W (by byte) Description Alarm second data register Reset Value 0x0
ALMSEC Reserved SECDATA
Bit [7] [6:4] [3:0]
Description BCD value for alarm second. 0~5 0~9
Initial State 0 000 0000
ALARM MIN DATA (ALMMIN) REGISTER Register ALMMIN Address 0x57000058(L) 0x5700005B(B) R/W R/W (by byte) Description Alarm minute data register Reset Value 0x00
ALMMIN Reserved MINDATA
Bit [7] [6:4] [3:0]
Description BCD value for alarm minute. 0~5 0~9
Initial State 0 000 0000
ALARM HOUR DATA (ALMHOUR) REGISTER Register ALMHOUR Address 0x5700005C(L) 0x5700005F(B) R/W R/W (by byte) Description Alarm hour data register Reset Value 0x0
ALMHOUR Reserved HOURDATA
Bit [7:6] [5:4] [3:0]
Description BCD value for alarm hour. 0~2 0~9
Initial State 00 00 0000
17-6
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
REAL TIME CLOCK
ALARM DATE DATA (ALMDATE) REGISTER Register ALMDATE Address 0x57000060(L) 0x57000063(B) R/W R/W (by byte) Description Alarm date data register Reset Value 0x01
ALMDATE Reserved DATEDATA
Bit [7:6] [5:4] [3:0]
Description BCD value for alarm date, from 0 to 28, 29, 30, 31. 0~3 0~9
Initial State 00 00 0001
ALARM MON DATA (ALMMON) REGISTER Register ALMMON Address 0x57000064(L) 0x57000067(B) R/W R/W (by byte) Description Alarm month data register Reset Value 0x01
ALMMON Reserved MONDATA
Bit [7:5] [4] [3:0]
Description BCD value for alarm month. 0~1 0~9
Initial State 00 0 0001
ALARM YEAR DATA (ALMYEAR) REGISTER Register ALMYEAR Address 0x57000068(L) 0x5700006B(B) R/W R/W (by byte) Description Alarm year data register Reset Value 0x0
ALMYEAR YEARDATA
Bit [7:0] BCD value for year. 00 ~ 99
Description
Initial State 0x0
17-7
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
REAL TIME CLOCK
S3C2440X RISC MICROPROCESSOR
RTC ROUND RESET (RTCRST) REGISTER Register RTCRST Address 0x5700006C(L) 0x5700006F(B) R/W R/W (by byte) Description RTC round reset register Reset Value 0x0
RTCRST SRSTEN SECCR
Bit [3] [2:0]
Description Round second reset enable. 0 = Disable, 1 = Enable Round boundary for second carry generation. 011 = over than 30 sec 100 = over than 40 sec 101 = over than 50 sec Note: If other values (0, 1, 2, 6, or 7) are set, no second carry is generated. But second value can be reset.
Initial State 0 000
BCD SECOND (BCDSEC) REGISTER Register BCDSEC Address 0x57000070(L) 0x57000073(B) R/W R/W (by byte) Description BCD second register Reset Value Undefined
BCDSEC SECDATA
Bit [6:4] [3:0] BCD value for second. 0~5 0~9
Description
Initial State -
BCD MINUTE (BCDMIN) REGISTER Register BCDMIN Address 0x57000074(L) 0x57000077(B) R/W R/W (by byte) Description BCD minute register Reset Value Undefined
BCDMIN MINDATA
Bit [6:4] [3:0] BCD value for minute. 0~5 0~9
Description
Initial State -
17-8
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
REAL TIME CLOCK
BCD HOUR (BCDHOUR) REGISTER Register BCDHOUR Address 0x57000078(L) 0x5700007B(B) R/W R/W (by byte) Description BCD hour register Reset Value Undefined
BCDHOUR Reserved HOURDATA
Bit [7:6] [5:4] [3:0]
Description BCD value for hour. 0~2 0~9
Initial State -
BCD DATE (BCDDATE) REGISTER Register BCDDATE Address 0x5700007C(L) 0x5700007F(B) R/W R/W (by byte) Description BCD date register Reset Value Undefined
BCDDATE Reserved DATEDATA
Bit [7:6] [5:4] [3:0] BCD value for date. 0~3 0~9
Description
Initial State -
BCD DAY (BCDDAY) REGISTER Register BCDDAY Address 0x57000080(L) 0x57000083(B) R/W R/W (by byte) Description BCD a day of the week register Reset Value Undefined
BCDDAY Reserved DAYDATA
Bit [7:3] [2:0]
Description BCD value for a day of the week. 1~7
Initial State -
17-9
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
REAL TIME CLOCK
S3C2440X RISC MICROPROCESSOR
BCD MONTH (BCDMON) REGISTER Register BCDMON Address 0x57000084(L) 0x57000087(B) R/W R/W (by byte) Description BCD month register Reset Value Undefined
BCDMON Reserved MONDATA
Bit [7:5] [4] [3:0]
Description BCD value for month. 0~1 0~9
Initial State -
BCD YEAR (BCDYEAR) REGISTER Register BCDYEAR Address 0x57000088(L) 0x5700008B(B) R/W R/W (by byte) Description BCD year register Reset Value Undefined
BCDYEAR YEARDATA
Bit [7:0]
Description BCD value for year. 00 ~ 99
Initial State -
17-10
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
WATCH-DOG TIMER
WATCHDOG TIMER
OVERVIEW
The S3C2440X watchdog timer is used to resume the controller operation whenever it is disturbed by malfunctions such as noise and system errors. It can be used as a normal 16-bit interval timer to request interrupt service. The watchdog timer generates the reset signal for 128 PCLK cycles. FEATURES -- Normal interval timer mode with interrupt request -- Internal reset signal is activated for 128 PCLK cycles when the timer count value reaches 0 (time-out).
18-1
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
WATCHDOG TIMER
S3C2440X RISC MICROPROCESSOR
WATCHDOG TIMER OPERATION Figure 18-1 shows the functional block diagram of the watchdog timer. The watchdog timer uses only PCLK as its source clock. The PCLK frequency is prescaled to generate the corresponding watchdog timer clock, and the resulting frequency is divided again.
MUX 1/16 1/32 PCLK 8-bit Prescaler 1/64 1/128
WTDAT Interrupt WTCNT (Down Counter)
Reset Signal Generator
RESET
WTCON[15:8]
WTCON[4:3]
WTCON[2]
WTCON[0]
Figure 18-1. Watchdog Timer Block Diagram The prescaler value and the frequency division factor are specified in the watchdog timer control (WTCON) register. Valid prescaler values range from 0 to 28-1. The frequency division factor can be selected as 16, 32, 64, or 128. Use the following equation to calculate the watchdog timer clock frequency and the duration of each timer clock cycle: t_watchdog = 1/[ PCLK / (Prescaler value + 1) / Division_factor ] WTDAT & WTCNT Once the watchdog timer is enabled, the value of watchdog timer data (WTDAT) register cannot be automatically reloaded into the timer counter (WTCNT). In this reason, an initial value must be written to the watchdog timer count (WTCNT) register, before the watchdog timer starts. CONSIDERATION OF DEBUGGING ENVIRONMENT When the S3C2440X is in debug mode using Embedded ICE, the watchdog timer must not operate. The watchdog timer can determine whether or not it is currently in the debug mode from the CPU core signal (DBGACK signal). Once the DBGACK signal is asserted, the reset output of the watchdog timer is not activated as the watchdog timer is expired.
18-2
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
WATCH-DOG TIMER
WATCHDOG TIMER SPECIAL REGISTERS
WATCHDOG TIMER CONTROL (WTCON) REGISTER The WTCON register allows the user to enable/disable the watchdog timer, select the clock signal from 4 different sources, enable/disable interrupts, and enable/disable the watchdog timer output. The Watchdog timer is used to resume the S3C2440X restart on mal-function after its power on; if controller restart is not desired, the Watchdog timer should be disabled. If the user wants to use the normal timer provided by the Watchdog timer, enable the interrupt and disable the Watchdog timer. Register WTCON Address 0x53000000 R/W R/W Description Watchdog timer control register Reset Value 0x8021
WTCON Prescaler value Reserved Watchdog timer
Bit [15:8] [7:6] [5]
Description Prescaler value. The valid range is from 0 to 255(28-1). Reserved. These two bits must be 00 in normal operation. Enable or disable bit of Watchdog timer. 0 = Disable 1 = Enable Determine the clock division factor. 00: 16 01 : 32 10: 64 11 : 128 Enable or disable bit of the interrupt. 0 = Disable 1 = Enable Reserved. This bit must be 0 in normal operation. Enable or disable bit of Watchdog timer output for reset signal. 1: Assert reset signal of the S3C2440X at watchdog timeout 0: Disable the reset function of the watchdog timer.
Initial State 0x80 00 1
Clock select
[4:3]
00
Interrupt generation
[2]
0
Reserved Reset enable/disable
[1] [0]
0 1
18-3
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
WATCHDOG TIMER
S3C2440X RISC MICROPROCESSOR
WATCHDOG TIMER DATA (WTDAT) REGISTER The WTDAT register is used to specify the time-out duration. The content of WTDAT cannot be automatically loaded into the timer counter at initial watchdog timer operation. However, using 0x8000 (initial value) will drive the first time-out. In this case, the value of WTDAT will be automatically reloaded into WTCNT. Register WTDAT Address 0x53000004 R/W R/W Description Watchdog timer data register Reset Value 0x8000
WTDAT Count reload value
Bit [15:0]
Description Watchdog timer count value for reload.
Initial State 0x8000
WATCHDOG TIMER COUNT (WTCNT) REGISTER The WTCNT register contains the current count values for the watchdog timer during normal operation. Note that the content of the WTDAT register cannot be automatically loaded into the timer count register when the watchdog timer is enabled initially, so the WTCNT register must be set to an initial value before enabling it. Register WTCNT Address 0x53000008 R/W R/W Description Watchdog timer count register Reset Value 0x8000
WTCNT Count value
Bit [15:0]
Description The current count value of the watchdog timer
Initial State 0x8000
18-4
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
SDI
SDI
OVERVIEW
The S3C2440X SDI(Secure Digital Interface) can interface for SD memory card, SDIO device and MMC(MultiMedia Card).
FEATURES -- SD Memory Card Spec(ver 1.0) / MMC Spec(2.11) compatible -- SDIO Card Spec(Ver 1.0) compatible -- 16 words(64 bytes) FIFO(depth 16) for data Tx/Rx -- 40-bit Command Register -- 136-bit Response Register -- 8-bit Prescaler logic(Freq = System Clock / (P + 1)) -- CRC7 & CRC16 generator -- Normal, and DMA data transfer mode(byte or word transfer) -- 1bit / 4bit(wide bus) mode & block / stream mode switch support
19-1
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
SDI
S3C2440X RISC MICROPROCESSOR
BLOCK DIAGRAM
32
PADDR
32
CMD Reg (5byte) Resp Reg (17byte)
8
CMD Control
8bit Shift Reg
TxCMD RxCMD
8
PSEL PCLK PWDATA 32 [31:0] PRDATA 32 [31:0] APB I/F
32
CRC7
Prescaler
32
SDCLK DAT Control
32bit Shift Reg
TxDAT[3:0] RxDAT[3:0]
32
FIFO (64byte)
32
CRC16*4
DREQ DACK INT
DMA INT
19-2
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X MICROPROCESSOR
SDI
SD OPERATION
A serial clock line synchronizes shifting and sampling of the information on the five data lines. The transmission frequency is controlled by making the appropriate bit settings to the SDIPRE register. You can modify its frequency to adjust the baud rate data register value. Programming Procedure (common) To program the SDI modules, follow these basic steps : 1. Set SDICON to configure properly with clock & interrupt enable 2. Set SDIPRE to configure with a proper value. 3. Wait 74 SDCLK clock cycle in order to initialize the card. CMD Path Programming 1. Write command argument 32bit to SDICARG. 2. Determine command types and start command transmit with setting SDICCON. 3. Confirm the end of SDI CMD path operation when the specific flag of SDICSTA is set 4. The flag is CmdSent if command type is no response. 5. The flag is RspFin if command type is with response. 6. Clear the corresponding flag of SDICSTA through writing one with this bit DAT Path Programming 1. Write data timeout period to SDIDTimer. 2. Write block size(block length) to SDIBSIZE(normally 0x80 word). 3. Determine the mode of block, wide bus, dma, etc and start data transfer with setting SDIDCON. 4. Tx data Write data to Data Register(SDIDAT) while Tx FIFO is available(TFDET is set), or half(TFHalf is set), or empty(TFEmpty is set). 5. Rx data Read data from Data Register(SDIDAT) while Rx FIFO is available(RFDET is set), or full(RFFull is set), or half(RFHalf is set), or ready for last data(RFLast is set). 6. Confirm the end of SDI DAT path operation when DatFin flag of SDIDSTA is set 7. Clear the corresponding flag of SDIDSTA through writing one with this bit
19-3
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
SDI
S3C2440X RISC MICROPROCESSOR
SDIO OPERATION
There are two functions of SDIO operation: SDIO Interrupt receiving and Read Wait Request generation. These two functions can operate when RcvIOInt bit and RwaitEn bit of SDICON register is activated respectively. And two functions have the steps and conditions below:SDIO Interrupt In SD 1bit mode, Interrupt is received through all range from RxDAT[1] pin. In SD 4bit mode, RxDAT[1] pin is shared between data receiving and interrupt receiving. When interrupt detection range(Interrupt Period) is : 1. Single Block : the time between A and B A : 2clocks after the completion of a data packet B : The completion of sending the end bit of the next with data command
2. Multi Block, PrdType = 0 : the time between A and B, restart at C A : 2clocks after the completion of a data packet B : 2clocks after A C : 2clocks after the end bit of the abort command response
3. Multi Block, PrdType = 1 : the time between A and B, restart at A A : 2clocks after the completion of a data packet B : 2clocks after A In case of last block, interrupt period begins at A, but not ends at B(CMD53 case)
Read Wait Request Regardless of 1bit or 4bit mode, Read Wait Request signal transmits to TxDAT[2] pin in condition of below. In read multiple operation, request signal transmission begins at 2clocks after the end of the data block Transmission ends when user sets to one RwaitReq bit of SDIDSTA register
-
19-4
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X MICROPROCESSOR
SDI
SDI SPECIAL REGISTERS
SDI Control Register(SDICON) Register SDICON SDICON Reserved Clock Type (CTYP) Byte Order Type(ByteOrder) Receive SDIO Interrupt from card (RcvIOInt) Read Wait Enable(RWaitEn) Address 0x5A000000 Bit [31:6] [5] [4] R/W R/W Description SDI Control Register Description Determines which clock type is used as SDCLK. 0 = SD type, 1 = MMC type Determines byte order type when you read(write) data from(to) sd host FIFO with word boundary. 0 = Type A, 1 = Type B Determines whether sd host receives SDIO Interrupt from the card or not(for SDIO). 0 = ignore, 1 = receive SDIO Interrupt Determines read wait request signal generate when sd host waits the next block in multiple block read mode. This bit needs to delay the next block to be transmitted from the card(for SDIO). 0 = disable(no generate), 1 = Read wait enable(use SDIO) Reset FIFO value. This bit is automatically clear. 0 = normal mode, 1 = FIFO reset Determines whether SDCLK Out enable or not 0 = disable(prescaler off), 1 = clock enable Reset Value 0x0 Initial Value 0 0
[3]
0
[2]
0
FIFO Reset(FRST) Clock Out Enable (ENCLK) * Byte Order Type
[1] [0]
0 0
- Type A : D[7:0] D[15:8] D[23:16] D[31:24] - Type B : D[31:24] D[23:16] D[15:8] D[7:0]
SDI Baud Rate Prescaler Register(SDIPRE) Register SDIPRE Address 0x5A000004 Bit [7:0] R/W R/W Description SDI Buad Rate Prescaler Register Reset Value 0x01 Initial Value 0x01
Description Determines SDI clock (SDCLK) rate as above equation. Baud rate = PCLK / (Prescaler value + 1) * Prescaler Value should be greater than zero. SDI Command Argument Register (SDICARG) Register SDICARG SDICARG CmdArg Address 0x5A000008 Bit [31:0] R/W R/W Description SDI Command Argument Register Description Command Argument
SDIPRE Prescaler Value
Reset Value 0x0 Initial Value 0x00000000
19-5
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
SDI
S3C2440X RISC MICROPROCESSOR
SDI Command Control Register (SDICCON) Register SDICCON SDICCON Reserved Abort Command (AbortCmd) Command with Data (WithData) LongRsp WaitRsp Command Start(CMST) CmdIndex Address 0x5A00000C Bit [31:13] [12] [11] [10] [9] [8] [7:0] R/W R/W Description SDI Command Control Register Description Determines whether command type is for abort(for SDIO). 0 = normal command, 1 = abort command(CMD12, CMD52) Determines whether command type is with data(for SDIO). 0 = without data, 1 = with data Determines whether host receives a 136-bit long response or not 0 = short response, 1 = long response Determines whether host waits for a response or not 0 = no response, 1 = wait response Determines whether command operation starts or not 0 = command ready, 1 = command start Command index with start 2bit(8bit) Reset Value 0x0 Initial Value 0 0 0 0 0 0x00
SDI Command Status Register (SDICSTA) Register SDICSTA SDICSTA Reserved Response CRC Fail(RspCrc) Command Sent (CmdSent) Command Time Out (CmdTout) Response Receive End (RspFin) CMD line progress On (CmdOn) RspIndex Address 0x5A000010 Bit [31:13] [12] R/C [11] R/C [10] R/C [9] R/C [8] [7:0] R/W R/(C) Description SDI Command Status Register Description CRC check failed when command response received. This flag is cleared by setting to one this bit. 0 = not detect, 1 = crc fail Command sent(not concerned with response). This flag is cleared by setting to one this bit. 0 = not detect, 1 = command end Command response timeout(64clk). This flag is cleared by setting to one this bit. 0 = not detect, 1 = timeout Command response received. This flag is cleared by setting to one this bit. 0 = not detect, 1 = response end Command transfer in progress 0 = not detect, 1 = in progress Response index 6bit with start 2bit(8bit) Reset Value 0x0 Initial Value 0
0
0
0
0 0x00
19-6
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X MICROPROCESSOR
SDI
SDI Response Register 0(SDIRSP0) Register SDIRSP0 SDIRSP0 Response0 Address 0x5A000014 Bit [31:0] R/W R Description SDI Response Register 0 Reset Value 0x0 Initial Value 0x00000000
Description Card status[31:0](short), card status[127:96](long)
SDI Response Register 1(SDIRSP1) Register SDIRSP1 SDIRSP1 RCRC7 Response1 Address 0x5A000018 Bit [31:24] [23:0] R/W R Description SDI Response Register 1 Reset Value 0x0 Initial Value 0x00 0x000000
Description CRC7(with end bit, short), card status[95:88](long) unused(short), card status[87:64](long)
SDI Response Register 2(SDIRSP2) Register SDIRSP2 SDIRSP2 Response2 Address 0x5A00001c Bit [31:0] R/W R Description SDI Response Register 2 Reset Value 0x0 Initial Value 0x00000000
Description unused(short), card status[63:32](long)
SDI Response Register 3(SDIRSP3) Register SDIRSP3 SDIRSP3 Response3 Address 0x5A000020 Bit [31:0] R/W R Description SDI Response Register 3 Reset Value 0x0 Initial Value 0x00000000
Description unused(short), card status[31:0](long)
19-7
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
SDI
S3C2440X RISC MICROPROCESSOR
SDI Data / Busy Timer Register(SDIDTimer) Register SDIDTimer SDIDTimer Reserved DataTimer Address 0x5A000024 Bit [31:23] [22:0] R/W R/W Description SDI Data / Busy Timer Register Description Data / Busy timeout period Reset Value 0x0 Initial Value 0x10000
SDI Block Size Register(SDIBSIZE) Register SDIBSIZE Address 0x5A000028 R/W R/W Description SDI Block Size Register Reset Value 0x0 Initial Value 0x000
SDIBSIZE Bit Description Reserved [31:12] BlkSize [11:0] Block Size value(0~4095 byte) , don't care when stream mode * In Case of multi block, BlkSize must be aligned to word(4byte) size.(BlkSize[1:0] = 00)
19-8
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X MICROPROCESSOR
SDI
SDI Data Control Register(SDIDCON) Register SDIDCON SDIDCON Reserved SDIO Interrupt Period Type (PrdType) Transmit After Response (TARSP) Receive After Command (RACMD) Busy After Command (BACMD) Block mode (BlkMode) Wide bus enable (WideBus) DMA Enable (EnDMA) Stop by force (STOP) Data Transfer Mode (DatMode) BlkNum Address 0x5A00002c Bit [31:22] [21] R/W R/W Description SDI Data control Register Description Determines whether SDIO Interrupt period is 2 cycle or extend more cycle when last data block is transferred(for SDIO). 0 = exactly 2 cycle, 1 = more cycle(likely single block) Determines when data transmit start after response receive or not 0 = directly after DatMode set, 1 = after response receive(assume DatMode sets to 2'b11) Determines when data receive start after command sent or not 0 = directly after DatMode set, 1 = after command sent (assume DatMode sets to 2'b10) Determines when busy receive start after command sent or not 0 = directly after DatMode set, 1 = after command sent (assume DatMode sets to 2'b01) Data transfer mode 0 = stream data transfer, 1 = block data transfer Determines enable wide bus mode 0 = standard bus mode(only SDIDAT[0] used), 1 = wide bus mode(SDIDAT[3:0] used) Enable DMA 0 = disable(polling), 1 = dma enable Determines whether data transfer stop by force or not 0 = normal, 1 = stop by force Determines which direction of data transfer 00 = ready, 01 = only busy check start 10 = data receive start, 11 = data transmit start Block Number(0~4095), don't care when stream mode Reset Value 0x0 Initial Value 0
[20]
0
[19]
0
[18]
0
[17] [16]
0 0
[15] [14] [13:12]
0 0 00
[11:0]
0x000
NOTES : 1. If you want one of TARSP, RACMD, BACMD bits(SDIDCON[20:18]) to "1", you need to write on SDIDCON register ahead of on SDICCON register.(always need for SDIO) 2. When DMA operation is completed, DMA Enable[15] bit of SDIDCON register should be disabled.
19-9
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
SDI
S3C2440X RISC MICROPROCESSOR
SDI Data Remain Counter Register(SDIDCNT) Register SDIDCNT SDIDCNT Reserved BlkNumCnt BlkCnt Address 0x5A000030 Bit [31:24] [23:12] [11:0] R/W R Description SDI Data Remain Counter Register Description Remaining Block number Remaining data byte of 1 block Reset Value 0x0 Initial Value 0x000 0x000
SDI Data Status Register(SDIDSTA) Register SDIDSTA SDIDSTA Reserved Read Wait Request Occur (RWaitReq) SDIO Interrupt Detect(IOIntDet) FIFO Fail error (FFfail) CRC Status Fail(CrcSta) Data Receive CRC Fail(DatCrc) Data Time Out(DatTout) Data Transfer Finish(DatFin) Busy Finish (BusyFin) Start Bit Error(SbitErr) Tx Data progress On(TxDatOn) Rx Data Progress On(RxDatOn) Address 0x5A000034 Bit [31:11] [10] R/C [9] R/C [8] R/C [7] R/C [6] R/C [5] R/C [4] R/C [3] R/C [2] R/C [1] [0] R/W R/(C) Description SDI Data Status Register Description Read wait request signal transmits to sd card. The request signal is stopped and this flag is cleared by setting to one this bit. 0 = not occur, 1 = Read wait request occur SDIO interrupt detect. This flag is cleared by setting to one this bit. 0 = not detect, 1 = SDIO interrupt detect FIFO fail error when FIFO occurs overrun / underrun / misaligned data saving. This flag is cleared by setting to one this bit. 0 = not detect, 1 = FIFO fail CRC Status error when data block sent(CRC check failed). This flag is cleared by setting to one this bit. 0 = not detect, 1 = crc status fail Data block received error(CRC check failed). This flag is cleared by setting to one this bit. 0 = not detect, 1 = receive crc fail Data / Busy receive timeout. This flag is cleared by setting to one this bit. 0 = not detect, 1 = timeout Data transfer completes(data counter is zero). This flag is cleared by setting to one this bit. 0 = not detect, 1 = data finish detect Only busy check finish. This flag is cleared by setting to one this bit 0 = not detect, 1 = busy finish detect Start bit is not detected on all data signals in wide bus mode. This flag is cleared by setting to one this bit. 0 = not detect, 1 = command end Data transmit in progress 0 = not active, 1 = data Tx in progress Data receive in progress 0 = not active, 1 = data Rx in progress Reset Value 0x0 Initial Value 0
0 0
0
0
0
0
0 0
0 0
19-10
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X MICROPROCESSOR
SDI
SDI FIFO Status Register(SDIFSTA) Register SDIFSTA SDIFSTA Reserved FIFO available Detect for Tx (TFDET) FIFO available Detect for Rx (RFDET) Tx FIFO Half Full (TFHalf) Tx FIFO Empty (TFEmpty) Rx FIFO Last Data Ready (RFLast) Rx FIFO Full (RFFull) Rx FIFO Half Full (RFHalf) FIFO Count (FFCNT) Address 0x5A000038 Bit [31:14] [13] R/W R Description SDI FIFO Status Register Description This bit indicates that FIFO data is available for transmit when DatMode is data transmit mode. If DMA mode is enable, sd host requests DMA operation. 0 = not detect(FIFO full), 1 = detect(0 FIFO 63) This bit indicates that FIFO data is available for receive when DatMode is data receive mode. If DMA mode is enable, sd host requests DMA operation. 0 = not detect(FIFO empty), 1 = detect(1 FIFO 64) This bit sets to 1 whenever Tx FIFO is less than 33byte. 0 = 33 Tx FIFO 64, 1 = 0 Tx FIFO 32 This bit sets to 1 whenever Tx FIFO is empty. 0 = 1 Tx FIFO 64, 1 = Empty(0byte) This bit sets to 1 whenever Rx FIFO has last data of all block. 0 = not received yet, 1 = Last data ready This bit sets to 1 whenever Rx FIFO is full. 0 = 0 Rx FIFO 63, 1 = Full(64byte) This bit sets to 1 whenever Rx FIFO is more than 31byte. 0 = 0 Rx FIFO 31, 1 = 32 Rx FIFO 64 Number of data(byte) in FIFO Reset Value 0x0 Initial State 0
[12]
0
[11] [10] [9] [8] [7] [6:0]
0 0 0 0 0 0000000
SDI Data Register(SDIDAT) Register SDIDAT Address 0x5A00003c(Li/W, Li/B, Bi/W) 0x5A00003f(Bi/B) Bit [31:0] R/W R/W Description SDI Data Register Reset Value 0x0
Description This field contains the data to be transmitted or received over the SDI channel * (Li/W, Li/B) : Access by Word/Byte unit when endian mode is Little * (Bi/W) : Access by Word unit when endian mode is Big * (Bi/B) : Access by Byte unit when endian mode is Big
SDIDAT Data Register
Initial State 0x00000000
19-11
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
SDI
S3C2440X RISC MICROPROCESSOR
SDI Interrupt Mask Register(SDIIMSK) Register SDIIMSK Address 0x5A000040 Bit [31:18] [17] [16] R/W R/W Description SDI Interrupt Mask Register Description Determines SDI generate an interrupt if response CRC check fails 0 = disable, 1 = interrupt enable Determines SDI generate an interrupt if command sent(no response required) 0 = disable, 1 = interrupt enable Determines SDI generate an interrupt if command response timeout occurs 0 = disable, 1 = interrupt enable Determines SDI generate an interrupt if command response received 0 = disable, 1 = interrupt enable Determines SDI generate an interrupt if read wait request occur. 0 = disable, 1 = interrupt enable Determines SDI generate an interrupt if sd host receives SDIO Interrupt from the card(for SDIO). 0 = disable, 1 = interrupt enable Determines SDI generate an interrupt if FIFO fail error occurs 0 = disable, 1 = interrupt enable Determines SDI generate an interrupt if CRC status error occurs 0 = disable, 1 = interrupt enable Determines SDI generate an interrupt if data receive CRC failed 0 = disable, 1 = interrupt enable Determines SDI generate an interrupt if data receive timeout occurs 0 = disable, 1 = interrupt enable Determines SDI generate an interrupt if data counter is zero 0 = disable, 1 = interrupt enable Determines SDI generate an interrupt if only busy check completes 0 = disable, 1 = interrupt enable Determines SDI generate an interrupt if start bit error detect 0 = disable, 1 = interrupt enable Determines SDI generate an interrupt if Tx FIFO fills half 0 = disable, 1 = interrupt enable Determines SDI generate an interrupt if Tx FIFO is empty 0 = disable, 1 = interrupt enable Determines SDI generate an interrupt if Rx FIFO has last data 0 = disable, 1 = interrupt enable Determines SDI generate an interrupt if Rx FIFO fills full 0 = disable, 1 = interrupt enable Determines SDI generate an interrupt if Rx FIFO fills half 0 = disable, 1 = interrupt enable Reset Value 0x0
Initial Value
SDICON Reserved RspCrc Interrupt Enable (RspCrcInt) CmdSent Interrupt Enable (CmdSentInt) CmdTout Interrupt Enable (CmdToutInt) RspEnd Interrupt Enable (RspEndInt) RWaitReq Interrupt Enable (RWReqInt) IOIntDet Interrupt Enable (IntDetInt) FFfail Interrupt Enable (FFfailInt) CrcSta Interrupt Enable (CrcStaInt) DatCrc Interrupt Enable (DatCrcInt) DatTout Interrupt Enable (DatToutInt) DatFin Interrupt Enable (DatFinInt) BusyFin Interrupt Enable(BusyFinInt) SBitErr Interrupt Enable (SBitErrInt) TFHalf Interrupt Enable (TFHalfInt) TFEmpty Interrupt Enable(TFEmptInt) RFLast Interrupt Enable (RFLastInt) RFFull Interrupt Enable (RFFullInt) RFHalf Interrupt Enable (RFHalfInt)
0 0
[15]
0
[14] [13] [12]
0 0 0
[11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
0 0 0 0 0 0 0 0 0 0 0 0
19-12
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X MICROPROCESSOR
SDI
NOTE
19-13
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
IIC-BUS INTERFACE
IIC-BUS INTERFACE
OVERVIEW
The S3C2440X RISC microprocessor can support a multi-master IIC-bus serial interface. A dedicated serial data line (SDA) and a serial clock line (SCL) carry information between bus masters and peripheral devices which are connected to the IIC-bus. The SDA and SCL lines are bi-directional. In multi-master IIC-bus mode, multiple S3C2440X RISC microprocessors can receive or transmit serial data to or from slave devices. The master S3C2440X can initiate and terminate a data transfer over the IIC-bus. The IIC-bus in the S3C2440X uses Standard bus arbitration procedure. To control multi-master IIC-bus operations, values must be written to the following registers: -- Multi-master IIC-bus control register, IICCON -- Multi-master IIC-bus control/status register, IICSTAT -- Multi-master IIC-bus Tx/Rx data shift register, IICDS -- Multi-master IIC-bus address register, IICADD When the IIC-bus is free, the SDA and SCL lines should be both at High level. A High-to-Low transition of SDA can initiate a Start condition. A Low-to-High transition of SDA can initiate a Stop condition while SCL remains steady at High Level. The Start and Stop conditions can always be generated by the master devices. A 7-bit address value in the first data byte, which is put onto the bus after the Start condition has been initiated, can determine the slave device which the bus master device has selected. The 8th bit determines the direction of the transfer (read or write). Every data byte put onto the SDA line should be eight bits in total. The bytes can be unlimitedly sent or received during the bus transfer operation. Data is always sent from most-significant bit (MSB) first, and every byte should be immediately followed by acknowledge (ACK) bit.
20-1
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
IIC-BUS INTERFACE
S3C2440X RISC MICROPROCESSOR
Address Register
Comparator IIC-Bus Control Logic SCL PCLK IICCON IICSTAT 4-bit Prescaler Shift Register SDA
Shift Register (IICDS)
Data Bus
Figure 20-1. IIC-Bus Block Diagram
20-2
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
IIC-BUS INTERFACE
IIC-BUS INTERFACE The S3C2440X IIC-bus interface has four operation modes: -- Master transmitter mode -- Master receive mode -- Slave transmitter mode -- Slave receive mode Functional relationships among these operating modes are described below. START AND STOP CONDITIONS When the IIC-bus interface is inactive, it is usually in Slave mode. In other words, the interface should be in Slave mode before detecting a Start condition on the SDA line (a Start condition can be initiated with a High-to-Low transition of the SDA line while the clock signal of SCL is High). When the interface state is changed to Master mode, a data transfer on the SDA line can be initiated and SCL signal generated. A Start condition can transfer a one-byte serial data over the SDA line, and a Stop condition can terminate the data transfer. A Stop condition is a Low-to-High transition of the SDA line while SCL is High. Start and Stop conditions are always generated by the master. The IIC-bus gets busy when a Start condition is generated. A Stop condition will make the IIC-bus free. When a master initiates a Start condition, it should send a slave address to notify the slave device. One byte of address field consists of a 7-bit address and a 1-bit transfer direction indicator (showing write or read). If bit 8 is 0, it indicates a write operation (transmit operation); if bit 8 is 1, it indicates a request for data read (receive operation). The master will finish the transfer operation by transmitting a Stop condition. If the master wants to continue the data transmission to the bus, it should generate another Start condition as well as a slave address. In this way, the read-write operation can be performed in various formats.
SDA
SDA
SCL
SCL
Start Condition
Stop Condition
Figure 20-2. Start and Stop Condition
20-3
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
IIC-BUS INTERFACE
S3C2440X RISC MICROPROCESSOR
DATA TRANSFER FORMAT Every byte placed on the SDA line should be eight bits in length. The bytes can be unlimitedly transmitted per transfer. The first byte following a Start condition should have the address field. The address field can be transmitted by the master when the IIC-bus is operating in Master mode. Each byte should be followed by an acknowledgement (ACK) bit. The MSB bit of the serial data and addresses are always sent first.
Write Mode Format with 7-bit Addresses S Slave Address 7bits R/W A "0" (Write) DATA(1Byte) AP
Data Transferred (Data + Acknowledge)
Write Mode Format with 10-bit Addresses S Slave Address 1st 7 bits 11110XX R/W A "0" (Write) Slave Address 2nd Byte A DATA AP
Data Transferred (Data + Acknowledge)
Read Mode Format with 7-bit Addresses S Slave Address 7 bits R/W A "1" (Read) DATA AP
Data Transferred (Data + Acknowledge)
Read Mode Format with 10-bit Addresses S Slave Address 1st 7 bits 11110XX R/W A "1" (Read) Slave Address 2nd Byte A rS Slave Address 1st 7 Bits R/W A "1" (Read) DATA AP
Data Transferred (Data + Acknowledge)
NOTES: 1. S: Start, rS: Repeat Start, P: Stop, A: Acknowledge 2. : From Master to Slave, : From Slave to Master
Figure 20-3. IIC-Bus Interface Data Format
20-4
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
IIC-BUS INTERFACE
SDA MSB Acknowledgement Signal from Receiver Acknowledgement Signal from Receiver
SCL S
1
2
7
8
9 ACK
1
2
9
Byte Complete, Interrupt within Receiver
Clock Line Held Low by receiver and/or transmitter
Figure 20-4. Data Transfer on the IIC-Bus
ACK SIGNAL TRANSMISSION To complete a one-byte transfer operation, the receiver should send an ACK bit to the transmitter. The ACK pulse should occur at the ninth clock of the SCL line. Eight clocks are required for the one-byte data transfer. The master should generate the clock pulse required to transmit the ACK bit. The transmitter should release the SDA line by making the SDA line High when the ACK clock pulse is received. The receiver should also drive the SDA line Low during the ACK clock pulse so that the SDA keeps Low during the High period of the ninth SCL pulse. The ACK bit transmit function can be enabled or disabled by software (IICSTAT). However, the ACK pulse on the ninth clock of SCL is required to complete the one-byte data transfer operation.
Clock to Output
Data Output by Transmitter
Data Output by Receiver
SCL from Master
S Start Condition
1
2
7
8
9
Clock Pulse for Acknowledgment
Figure 20-5. Acknowledge on the IIC-Bus
20-5
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
IIC-BUS INTERFACE
S3C2440X RISC MICROPROCESSOR
READ-WRITE OPERATION In Transmitter mode, when the data is transferred, the IIC-bus interface will wait until IIC-bus Data Shift (IICDS) register receives a new data. Before the new data is written into the register, the SCL line will be held low, and then released after it is written. The S3C2440X should hold the interrupt to identify the completion of current data transfer. After the CPU receives the interrupt request, it should write a new data into the IICDS register, again. In Receive mode, when data is received, the IIC-bus interface will wait until IICDS register is read. Before the new data is read out, the SCL line will be held low and then released after it is read. The S3C2440X should hold the interrupt to identify the completion of the new data reception. After the CPU receives the interrupt request, it should read the data from the IICDS register. BUS ARBITRATION PROCEDURES Arbitration takes place on the SDA line to prevent the contention on the bus between two masters. If a master with a SDA High level detects the other master with a SDA active Low level, it will not initiate a data transfer because the current level on the bus does not correspond to its own. The arbitration procedure will be extended until the SDA line turns High. However, when the masters simultaneously lower the SDA line, each master should evaluate whether or not the mastership is allocated to itself. For the purpose of evaluation, each master should detect the address bits. While each master generates the slaver address, it should also detect the address bit on the SDA line because the SDA line is likely to get Low rather than to keep High. Assume that one master generates a Low as first address bit, while the other master is maintaining High. In this case, both masters will detect Low on the bus because the Low status is superior to the High status in power. When this happens, Low (as the first bit of address) generating master will get the mastership while High (as the first bit of address) generating master should withdraw the mastership. If both masters generate Low as the first bit of address, there should be arbitration for the second address bit, again. This arbitration will continue to the end of last address bit. ABORT CONDITIONS If a slave receiver cannot acknowledge the confirmation of the slave address, it should hold the level of the SDA line High. In this case, the master should generate a Stop condition and to abort the transfer. If a master receiver is involved in the aborted transfer, it should signal the end of the slave transmit operation by canceling the generation of an ACK after the last data byte received from the slave. The slave transmitter should then release the SDA to allow a master to generate a Stop condition. CONFIGURING IIC-BUS To control the frequency of the serial clock (SCL), the 4-bit prescaler value can be programmed in the IICCON register. The IIC-bus interface address is stored in the IIC-bus address (IICADD) register. (By default, the IIC-bus interface address has an unknown value.)
20-6
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
IIC-BUS INTERFACE
FLOWCHARTS OF OPERATIONS IN EACH MODE The following steps must be executed before any IIC Tx/Rx operations. 1) Write own slave address on IICADD register, if needed. 2) Set IICCON register. a) Enable interrupt b) Define SCL period 3) Set IICSTAT to enable Serial Output
START Master Tx mode has been configured. Write slave address to IICDS. Write 0xF0 (M/T Start) to IICSTAT. The data of the IICDS is transmitted. ACK period and then interrupt is pending. Y
Stop? N
Write new data transmitted to IICDS. Clear pending bit to resume. The data of the IICDS is shifted to SDA.
Write 0xD0 (M/T Stop) to IICSTAT.
Clear pending bit .
Wait until the stop condition takes effect. END
Figure 20-6 Operations for Master/Transmitter Mode
20-7
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
IIC-BUS INTERFACE
S3C2440X RISC MICROPROCESSOR
START Master Rx mode has been configured. Write slave address to IICDS. Write 0xB0 (M/R Start) to IICSTAT. The data of the IICDS (slave address) is transmitted. ACK period and then interrupt is pending. Y
Stop?
N Read a new data from IICDS. Clear pending bit to resume.
Write 0x90 (M/R Stop) to IICSTAT.
Clear pending bit .
SDA is shifted to IICDS.
Wait until the stop condition takes effect. END
Figure 20-7 Operations for Master/Receiver Mode
20-8
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
IIC-BUS INTERFACE
START Slave Tx mode has been configured. IIC detects start signal. and, IICDS receives data. IIC compares IICADD and IICDS (the received slave address). N
Matched? Y
The IIC address match interrupt is generated.
Write data to IICDS.
Clear pending bit to resume. Y
Stop? N
The data of the IICDS is shifted to SDA.
END
Interrupt is pending.
Figure 20-8 Operations for Slave/Transmitter Mode
20-9
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
IIC-BUS INTERFACE
S3C2440X RISC MICROPROCESSOR
START Slave Rx mode has been configured. IIC detects start signal. and, IICDS receives data. IIC compares IICADD and IICDS (the received slave address). N
Matched? Y
The IIC address match interrupt is generated.
Read data to IICDS.
Clear pending bit to resume. Y
Stop? N
SDA is shifted to IICDS.
END
Interrupt is pending.
Figure 20-9 Operations for Slave/Receiver Mode
20-10
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
IIC-BUS INTERFACE
IIC-BUS INTERFACE SPECIAL REGISTERS
MULTI-MASTER IIC-BUS CONTROL (IICCON) REGISTER Register IICCON Address 0x54000000 R/W R/W Description IIC-Bus control register Reset Value 0x0X
IICCON Acknowledge generation (1)
Bit [7] 0 : Disable 1 : Enable
Description IIC-bus acknowledge enable bit.
Initial State 0
In Tx mode, the IICSDA is free in the ack time. In Rx mode, the IICSDA is L in the ack time. Tx clock source selection [6] Source clock of IIC-bus transmit clock prescaler selection bit. 0 : IICCLK = fPCLK /16 1 : IICCLK = fPCLK /512 Tx/Rx Interrupt (5) Interrupt pending flag
(2) (3)
0
[5] [4]
IIC-Bus Tx/Rx interrupt enable/disable bit. 0 : Disable, 1 : Enable IIC-bus Tx/Rx interrupt pending flag. This bit cannot be written to 1. When this bit is read as 1, the IICSCL is tied to L and the IIC is stopped. To resume the operation, clear this bit as 0. 0 : 1) No interrupt pending (when read). 2) Clear pending condition & Resume the operation (when write). 1 : 1) Interrupt is pending (when read) 2) N/A (when write)
0 0
Transmit clock value (4)
[3:0]
IIC-Bus transmit clock prescaler. IIC-Bus transmit clock frequency is determined by this 4-bit prescaler value, according to the following formula: Tx clock = IICCLK/(IICCON[3:0]+1).
Undefined
Notes: 1. Interfacing with EEPROM, the ack generation may be disabled before reading the last data in order to generate the STOP condition in Rx mode. 2. An IIC-bus interrupt occurs 1) when a 1-byte transmit or receive operation is completed, 2) when a general call or a slave address match occurs, or 3) if bus arbitration fails. 3. To adjust the setup time of IICSDA before IISSCL rising edge, IICDS has to be written before clearing the IIC interrupt pending bit. 4. IICCLK is determined by IICCON[6]. Tx clock can vary by SCL transition time. When IICCON[6]=0, IICCON[3:0]=0x0 or 0x1 is not available. 5. If the IICON[5]=0, IICON[4] does not operate correctly. So, It is recommended that you should set IICCON[5]=1, although you does not use the IIC interrupt.
20-11
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
IIC-BUS INTERFACE
S3C2440X RISC MICROPROCESSOR
MULTI-MASTER IIC-BUS CONTROL/STATUS (IICSTAT) REGISTER Register IICSTAT Address 0x54000004 R/W R/W Description IIC-Bus control/status register Reset Value 0x0
IICSTAT Mode selection
Bit [7:6]
Description IIC-bus master/slave Tx/Rx mode select bits. 00 : Slave receive mode 01 : Slave transmit mode 10 : Master receive mode 11 : Master transmit mode
Initial State 00
Busy signal status / START STOP condition
[5]
IIC-Bus busy signal status bit. 0 : read) Not busy (when read) write) STOP signal generation 1 : read) Busy (when read) write) START signal generation. The data in IICDS will be transferred automatically just after the start signal.
0
Serial output Arbitration status flag
[4] [3]
IIC-bus data output enable/disable bit. 0 : Disable Rx/Tx, 1 : Enable Rx/Tx IIC-bus arbitration procedure status flag bit. 0 : Bus arbitration successful 1 : Bus arbitration failed during serial I/O
0 0
Address-as-slave status flag
[2]
IIC-bus address-as-slave status flag bit. 0 : Cleared when START/STOP condition was detected 1 : Received slave address matches the address value in the IICADD
0
Address zero status flag
[1]
IIC-bus address zero status flag bit. 0 : Cleared when START/STOP condition was detected 1 : Received slave address is 00000000b.
0
Last-received bit status flag
[0]
IIC-bus last-received bit status flag bit. 0 : Last-received bit is 0 (ACK was received). 1 : Last-received bit is 1 (ACK was not received).
0
20-12
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
IIC-BUS INTERFACE
MULTI-MASTER IIC-BUS ADDRESS (IICADD) REGISTER Register IICADD Address 0x54000008 R/W R/W Description IIC-Bus address register Reset Value 0xXX
IICADD Slave address
Bit [7:0]
Description 7-bit slave address, latched from the IIC-bus. When serial output enable = 0 in the IICSTAT, IICADD is write-enabled. The IICADD value can be read any time, regardless of the current serial output enable bit (IICSTAT) setting. Slave address : [7:1] Not mapped : [0]
Initial State XXXXXXXX
MULTI-MASTER IIC-BUS TRANSMIT/RECEIVE DATA SHIFT (IICDS) REGISTER Register IICDS Address 0x5400000C R/W R/W Description IIC-Bus transmit/receive data shift register Reset Value 0xXX
IICDS Data shift
Bit [7:0]
Description 8-bit data shift register for IIC-bus Tx/Rx operation. When serial output enable = 1 in the IICSTAT, IICDS is write-enabled. The IICDS value can be read any time, regardless of the current serial output enable bit (IICSTAT) setting.
Initial State XXXXXXXX
20-13
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
IIC-BUS INTERFACE
S3C2440X RISC MICROPROCESSOR
MULTI-MASTER IIC-BUS LINE CONTROL(IICLC) REGISTER Register IICLC Address 0x54000010 R/W R/W Description IIC-Bus multi-master line control register Reset Value 0x00
IICLC Filter Enable
Bit [2]
Description IIC-bus filter enable bit. When SDA port is operating as input, the filter enable bit should be High. This filter can prevent from occurred error by a glitch during double of PCLK time. 0 : Filter disable 1 : Filter enable
Initial State 0
SDA output delay
[1:0]
IIC-Bus SDA line delay length selection bits. It is delayed for following clock time(PCLK) after High-to-Low transition of SCL line is occurred. Then a High-to-Low transition of the SDA line will be occurred. 00 : 0 clocks 10 : 10 clocks 01 : 5 clocks 11 : 15 clocks
00
20-14
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
IIS-BUS INTERFACE
21
OVERVIEW
IIS-BUS INTERFACE
Currently, many digital audio systems are attracting the consumers on the market, in the form of compact discs, digital audio tapes, digital sound processors, and digital TV sound. The S3C2440X Inter-IC Sound (IIS) bus interface can be used to implement a CODEC interface to an external 8/16-bit stereo audio CODEC IC for minidisc and portable applications. The IIS bus interface supports both IIS bus data format and MSB-justified data format. The interface provides DMA transfer mode for FIFO access instead of an interrupt. It can transmit and receive data simultaneously as well as transmit or receive data alternatively at a time.
21-1
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
IIS-BUS INTERFACE
S3C2440X RISC MICROPROCESSOR
BLOCK DIAGRAM
ADDR DATA CNTL BRFC
TxFIFO SFTR RxFIFO CHNC SD
IPSR_A PCLK SCLKG IPSR_B
SCLK LRCK
CDCLK
Figure 21-1. IIS-Bus Block Diagram
FUNCTIONAL DESCRIPTIONS
Bus interface, register bank, and state machine (BRFC): Bus interface logic and FIFO access are controlled by the state machine. 5-bit dual prescaler (IPSR): One prescaler is used as the master clock generator of the IIS bus interface and the other is used as the external CODEC clock generator. 64-byte FIFOs (TxFIFO and RxFIFO): In transmit data transfer, data are written to TxFIFO, and, in the receive data transfer, data are read from RxFIFO. Master IISCLK generator (SCLKG): In master mode, serial bit clock is generated from the master clock. Channel generator and state machine (CHNC): IISCLK and IISLRCK are generated and controlled by the channel state machine. 16-bit shift register (SFTR): Parallel data is shifted to serial data output in the transmit mode, and serial data input is shifted to parallel data in the receive mode. TRANSMIT OR RECEIVE ONLY MODE Normal transfer IIS control register has FIFO ready flag bits for transmit and receive FIFOs. When FIFO is ready to transmit data, the FIFO ready flag is set to '1' if transmit FIFO is not empty. If transmit FIFO is empty, FIFO ready flag is set to '0'. When receive FIFO is not full, the FIFO ready flag for receive FIFO is set to '1' ; it indicates that FIFO is ready to receive data. If receive FIFO is full, FIFO ready flag is set to '0'. These flags can determine the time that CPU is to write or read FIFOs. Serial data can be transmitted or received while the CPU is accessing transmit and receive FIFOs in this way.
21-2
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
IIS-BUS INTERFACE
DMA TRANSFER In this mode, transmit or receive FIFO is accessible by the DMA controller. DMA service request in transmit or receive mode is made by the FIFO ready flag automatically. TRANSMIT AND RECEIVE MODE In this mode, IIS bus interface can transmit and receive data simultaneously.
AUDIO SERIAL INTERFACE FORMAT
IIS-BUS FORMAT The IIS bus has four lines including serial data input (IISDI), serial data output (IISDO), left/right channel select (IISLRCK), and serial bit clock (IISCLK); the device generating IISLRCK and IISCLK is the master. Serial data is transmitted in 2's complement with the MSB first. The MSB is transmitted first because the transmitter and receiver may have different word lengths. The transmitter does not have to know how many bits the receiver can handle, nor does the receiver need to know how many bits are being transmitted. When the system word length is greater than the transmitter word length, the word is truncated (least significant data bits are set to '0') for data transmission. If the receiver gets more bits than its word length, the bits after the LSB are ignored. On the other hand, if the receiver gets fewer bits than its word length, the missing bits are set to zero internally. And therefore, the MSB has a fixed position, whereas the position of the LSB depends on the word length. The transmitter sends the MSB of the next word at one clock period whenever the IISLRCK is changed. Serial data sent by the transmitter may be synchronized with either the trailing (HIGH to LOW) or the leading (LOW to HIGH) edge of the clock signal. However, the serial data must be latched into the receiver on the leading edge of the serial clock signal, and so there are some restrictions when transmitting data that is synchronized with the leading edge. The LR channel select line indicates the channel being transmitted. IISLRCK may be changed either on a trailing or leading edge of the serial clock, but it does not need to be symmetrical. In the slave, this signal is latched on the leading edge of the clock signal. The IISLRCK line changes one clock period before the MSB is transmitted. This allows the slave transmitter to derive synchronous timing of the serial data that will be set up for transmission. Furthermore, it enables the receiver to store the previous word and clear the input for the next word. MSB (LEFT) JUSTIFIED MSB / left justified bus format is the same as IIS bus format architecturally. Only, different from the IIS bus format, the MSB justified format realizes that the transmitter always sends the MSB of the next word whenever the IISLRCK is changed.
21-3
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
IIS-BUS INTERFACE
S3C2440X RISC MICROPROCESSOR
LRCK
LEFT
RIGHT
LEFT
SCLK
MSB (1st) 2nd Bit N-1th Bit LSB (last) MSB (1st) 2nd Bit N-1th Bit LSB (last) MSB (1st)
SD
IIS-bus Format (N=8 or 16)
LRCK
LEFT
RIGHT
SCLK
MSB (1st) 2nd Bit N-1th Bit LSB (last) MSB (1st) 2nd Bit N-1th Bit LSB (last)
SD
MSB-justified Format (N=8 or 16)
Figure 21-2. IIS-Bus and MSB (Left)-justified Data Interface Formats SAMPLING FREQUENCY AND MASTER CLOCK Master clock frequency (PCLK) can be selected by sampling frequency as shown in Table 21-1. Because PCLK is made by IIS prescaler, the prescaler value and PCLK type (256 or 384fs) should be determined properly. Serial bit clock frequency type (16/32/48fs) can be selected by the serial bit per channel and PCLK as shown in Table 21-2. Table 21-1 CODEC clock (CODECLK = 256 or 384fs) IISLRCK (fs) CODECLK (MHz) 8.000 KHz 256fs 2.0480 384fs 3.0720 4.2336 6.1440 8.4672 12.2880 16.9344 18.4320 24.5760 33.8688 36.8640 2.8224 4.0960 5.6448 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760 11.025 KHz 16.000 KHz 22.050 KHz 32.000 KHz 44.100 KHz 48.000 KHz 64.000 KHz 88.200 KHz 96.000 KHz
Table 21-2 Usable serial bit clock frequency (IISCLK = 16 or 32 or 48fs) Serial bit per channel Serial clock frequency (IISCLK) @CODECLK = 256fs @CODECLK = 384fs 16fs, 32fs 16fs, 32fs, 48fs 32fs 32fs, 48fs 8-bit 16-bit
21-4
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
IIS-BUS INTERFACE
IIS-BUS INTERFACE SPECIAL REGISTERS
IIS CONTROL (IISCON) REGISTER Register IISCON Address 0x55000000 (Li/HW, Li/W, Bi/W) 0x55000002 (Bi/HW) R/W R/W Description IIS control register Reset Value 0x100
IISCON Left/Right channel index (Read only) Transmit FIFO ready flag (Read only) Receive FIFO ready flag (Read only) Transmit DMA service request Receive DMA service request Transmit channel idle command
Bit [8] [7] [6] [5] [4] [3] 0 = Left 1 = Right
Description
Initial State 1 0 0 0 0 0
0 = Not ready (empty) 1 = Ready (not empty) 0 = Not ready (full) 1 = Ready (not full) 0 = Disable 1 = Enable 0 = Disable 1 = Enable In Idle state the IISLRCK is inactive (Pause Tx). 0 = Not idle 1 = Idle In Idle state the IISLRCK is inactive (Pause Rx). 0 = Not idle 1 = Idle 0 = Disable 1 = Enable 0 = Disable (stop) 1 = Enable (start)
Receive channel idle command
[2]
0
IIS prescaler IIS interface
[1] [0]
0 0
Notes: 1. The IISCON register is accessible for each byte, halfword and word unit using STRB/STRH/STR and LDRB/LDRH/LDR instructions or char/short int/int type pointer in Little/Big endian mode. 2. (Li/HW/W) : Little/HalfWord/Word (Bi/HW/W) : Big/HalfWord/Word
21-5
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
IIS-BUS INTERFACE
S3C2440X RISC MICROPROCESSOR
IIS MODE REGISTER (IISMOD) REGISTER Register IISMOD Address 0x55000004 (Li/W, Li/HW, Bi/W) 0x55000006 (Bi/HW) R/W R/W Description IIS mode register Reset Value 0x0
IISMOD Master/slave mode select
Bit [8]
Description 0 = Master mode (IISLRCK and IISCLK are output mode). 1 = Slave mode (IISLRCK and IISCLK are input mode). 00 = No transfer 10 = Transmit mode 01 = Receive mode 11 = Transmit and receive mode
Initial State 0
Transmit/receive mode select Active level of left/right channel Serial interface format Serial data bit per channel Master clock frequency select Serial bit clock frequency select
[7:6] [5] [4] [3] [2] [1:0]
00 0 0 0 0 00
0 = Low for left channel (High for right channel) 1 = High for left channel (Low for right channel) 0 = IIS compatible format 1 = MSB (Left)-justified format 0 = 8-bit 1 = 16-bit 0 = 256fs 1 = 384fs (fs : sampling frequency) 00 = 16fs 10 = 48fs 01 = 32fs 11 = N/A
Notes: 1. The IISMOD register is accessible for each halfword and wordunit using STRH/STR and LDRH/LDR instructions or short int/int type pointer in Little/Big endian mode. 2. (Li/HW/W) : Little/HalfWord/Word. (Bi/HW/W) : Big/HalfWord/Word.
21-6
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
IIS-BUS INTERFACE
IIS PRESCALER (IISPSR) REGISTER Register IISPSR Address 0x55000008 (Li/HW, Li/W, Bi/W) 0x5500000A (Bi/HW) R/W R/W Description IIS prescaler register Reset Value 0x0
IISPSR Prescaler control A
Bit [9:5] Data value: 0 ~ 31
Description Note: Prescaler A makes the master clock that is used the internal block and division factor is N+1.
Initial State 00000
Prescaler control B
[4:0]
Data value: 0 ~ 31 Note: Prescaler B makes the master clock that is used the external block and division factor is N+1.
00000
Notes: 1. The IISPSR register is accessible for each byte, halfword and word unit using STRB/STRH/STR and LDRB/LDRH/LDR instructions or char/short int/int type pointer in Little/Big endian mode. 2. (Li/HW/W) : Little/HalfWord/Word. (Bi/HW/W) : Big/HalfWord/Word.
21-7
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
IIS-BUS INTERFACE
S3C2440X RISC MICROPROCESSOR
IIS FIFO CONTROL (IISFCON) REGISTER Register IISFCON Address 0x5500000C (Li/HW, Li/W, Bi/W) 0x5500000E (Bi/HW) R/W R/W Description IIS FIFO interface register Reset Value 0x0
IISFCON Transmit FIFO access mode select Receive FIFO access mode select Transmit FIFO Receive FIFO Transmit FIFO data count (Read only) Receive FIFO data count (Read only)
Bit [15] [14] [13] [12] [11:6] [5:0] 0 = Normal 1 = DMA 0 = Normal 1 = DMA 0 = Disable 0 = Disable
Description
Initial State 0 0
1 = Enable 1 = Enable
0 0 000000 000000
Data count value = 0 ~ 32 Data count value = 0 ~ 32
NOTES: 1. The IISFCON register is accessible for each halfword and word unit using STRH/STR and LDRH/LDR instructions or short int/int type pointer in Little/Big endian mode. 2. (Li/HW/W): Little/HalfWord/Word. (Bi/HW/W): Big/HalfWord/Word.
IIS FIFO (IISFIFO) REGISTER IIS bus interface contains two 16-byte FIFO for the transmit and receive mode. Each FIFO has 16-width and 24depth form, which allows the FIFO to handles data for each halfword unit regardless of valid data size. Transmit and receive FIFO access is performed through FIFO entry; the address of FENTRY is 0x55000010. Register IISFIFO Address 0x55000010(Li/HW) 0x55000012(Bi/HW) R/W R/W Description IIS FIFO register Reset Value 0x0
IISFIF FENTRY
Bit [15:0]
Description Transmit/Receive data for IIS
Initial State 0x0
NOTES: 1. The IISFIFO register is accessible for each halfword and word unit using STRH and LDRH instructions or short int type pointer in Little/Big endian mode. 2. (Li/HW): Little/HalfWord. (Bi/HW): Big/HalfWord.
21-8
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
SPI
22
OVERVIEW
SPI
The S3C2440X Serial Peripheral Interface (SPI) can interface the serial data transfer. The S3C2440X includes two SPI, each of which has two 8-bit shift registers for transmission and receiving, respectively. During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). 8-bit serial data at a frequency is determined by its corresponding control register settings. If you only want to transmit, received data can be dummy. Otherwise, if you only want to receive, you should transmit dummy '1' data. There are 4 I/O pin signals associated with SPI transfers: the SCK (SPICLK0,1), the MISO (SPIMISO0,1) data line, the MOSI (SPIMOSI0,1) data line, and the active low /SS (nSS0,1) pin (input).
FEATURES -- Support 2-ch SPI -- SPI Protocol (ver. 2.11) compatible -- 8-bit Shift Register for transmit -- 8-bit Shift Register for receive -- 8-bit Prescaler logic -- Polling, Interrupt, and DMA transfer mode -- 5V tolerant input (SPI channel 1)
22-1
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
SPI
S3C2440X RISC MICROPROCESSOR
BLOCK DIAGRAM
Data Bus
8
LSB
MSB
SPIMISO 0 Slave Master Master Slave Clock MISO
Tx 8bit Shift Reg 0
Rx 8bit Shift Reg 0
Pin Control Logic 0
8
MSB
LSB
SPIMOSI 0 MOSI
PCLK
8bit Prescaler 0
SPI Clock (Master) CPOL CPHA
CLOCK Logic 0
SPICLK 0 SCK
Slave Master
Prescaler Register 0 Status Register 0
DCOL REDY MULF
nSS 0 Slave /SS
INT 0 / INT 1 REQ0 / REQ1 ACK0 / ACK1
MSTR
APB I/F 0
(INT DMA 0)
8
LSB
MSB
SPIMISO 1 Slave Master Master Slave Clock MISO
Tx 8bit Shift Reg 1
Rx 8bit Shift Reg 1
Pin Control Logic 1
8
MSB
LSB
SPIMOSI 1 MOSI
PCLK
8bit Prescaler 1
SPI Clock (Master) CPOL CPHA
CLOCK Logic 1
SPICLK 1 SCK
Slave Master
Prescaler Register 1 Status Register 1
DCOL MULF REDY
nSS 1 Slave /SS
INT 0 / INT 1 REQ0 / REQ1 ACK0 / ACK1
MSTR
APB I/F 1
(INT DMA 1)
Figure 22-1. SPI Block Diagram
22-2
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
SPI
SPI OPERATION
Using the SPI interface, the S3C2440X can send/receive 8 -bit data simultaneously with an external device. A serial clock line is synchronized with the two data lines for shifting and sampling of the information. When the SPI is the master, transmission frequency can be controlled by setting the appropriate bit to SPPREn register. You can modify its frequency to adjust the baud rate data register value. When the SPI is a slave, other master supplies the clock. When the programmer writes byte data to SPTDATn register, SPI transmit/receive operation will start simultaneously. In some cases, nSS should be activated before writing byte data to SPTDATn. Programming Procedure When a byte data is written into the SPTDATn register, SPI starts to transmit if ENSCK and MSTR of SPCONn register are set. You can use a typical programming procedure to operate an SPI card. To program the SPI modules, follow these basic steps: 1. Set Baud Rate Prescaler Register (SPPREn). 2. Set SPCONn to configure properly the SPI module. 3. Write data 0xFF to SPTDATn 10 times in order to initialize MMC or SD card. 4. Set a GPIO pin, which acts as nSS, to low to activate the MMC or SD card. 5. Tx data Check the status of Transfer Ready flag (REDY=1), and then write data to SPTDATn. 6. Rx data(1): SPCONn's TAGD bit disable = normal mode write 0xFF to SPTDATn, then confirm REDY to set, and then read data from Read Buffer. 7. Rx data(2): SPCONn's TAGD bit enable = Tx Auto Garbage Data mode confirm REDY to set, and then read data from Read Buffer(then automatically start to transfer). 8. Set a GPIO pin, which acts as nSS, to high, to deactivate MMC or SD card.
22-3
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
SPI
S3C2440X RISC MICROPROCESSOR
SPI Transfer Format The S3C2440X supports 4 different format to transfer the data. Figure 22-2 shows four waveforms for SPICLK..
CPOL = 0, CPHA = 0 (Format A) Cycle SPICLK MOSI MISO MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB MSB* 1 2 3 4 5 6 7 8
* MSB of character just received CPOL = 0, CPHA = 1 (Format B) Cycle SPICLK MOSI MISO *LSB MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB* 1 2 3 4 5 6 7 8
* LSB of previously transmitted character CPOL = 1, CPHA = 0 (Format A) Cycle SPICLK MOSI MISO MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB MSB* 1 2 3 4 5 6 7 8
* MSB of character just received CPOL = 1, CPHA = 1 (Format B) Cycle SPICLK MOSI MISO *LSB MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB 1 2 3 4 5 6 7 8
* LSB of previously transmitted character
Figure 22-2. SPI Transfer Format
22-4
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
SPI
Transmitting procedure by DMA 1. The SPI is configured as DMA mode. 2. DMA is configured properly. 3. The SPI requests DMA service. 4. DMA transmits 1byte data to the SPI. 5. The SPI transmits the data to card. 6. Return to Step 3 until DMA count becomes 0. 7. The SPI is configured as interrupt or polling mode with SMOD bits.
Receiving procedure by DMA 1. The SPI is configured as DMA start with SMOD bits and setting TAGD bit. 2. DMA is configured properly. 3. The SPI receives 1byte data from card. 4. The SPI requests DMA service. 5. DMA receives the data from the SPI. 6. Write data 0xFF automatically to SPTDATn. 7. Return to Step 4 until DMA count becomes 0. 8. The SPI is configured as polling mode with SMOD bits and clearing TAGD bit. 9. If SPSTAn's REDY flag is set, then read the last byte data. Note: Total received data = DMA TC values + the last data in polling mode (Step 9). The first DMA received data is dummy and so the user can neglect it.
22-5
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
SPI
S3C2440X RISC MICROPROCESSOR
SPI SPECIAL REGISTERS
SPI CONTROL REGISTER Register SPCON0 SPCON1 SPCONn SPI Mode Select (SMOD) SCK Enable (ENSCK) Master/Slave Select (MSTR) [3] Address 0x59000000 0x59000020 Bit [6:5] 00 = polling mode 10 = DMA mode [4] 0 = disable 0 = slave R/W R/W R/W Description SPI channel 0 control register SPI channel 1 control register Description Determine how and by what SPTDAT is read/written. 01 = interrupt mode 11 = reserved 0 0 1 = enable 1 = master Reset Value 0x00 0x00 Initial State 00
Determine whether you want SCK enable or not (for only master). Determine the desired mode (master or slave). Note: In slave mode, there should be set up time for master to initiate Tx/Rx.
Clock Polarity Select (CPOL) Clock Phase Select (CPHA) Tx Auto Garbage Data mode enable (TAGD)
[2] [1] [0]
Determine an active high or active low clock. 0 = active high 0 = format A 0 = normal mode 1 = active low Select one of two fundamentally different transfer formats. 1 = format B Decide whether the receiving data only needs or not. 1 = Tx auto garbage data mode Note: In normal mode, if you only want to receive data, you should transmit dummy 0xFF data.
0 0 0
22-6
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
SPI
SPI STATUS REGISTER Register SPSTA0 SPSTA1 SPSTAn Reserved Data Collision Error Flag (DCOL) Multi Master Error Flag (MULF) Address 0x59000004 0x59000024 Bit [7:3] [2] This flag is set if the SPTDATn is written or the SPRDATn is read while a transfer is in progress and cleared by reading the SPSTAn. 0 = not detect [1] 1 = collision error detect 0 This flag is set if the nSS signal goes to active low while the SPI is configured as a master, and SPPINn's ENMUL bit is multi master errors detect mode. MULF is cleared by reading SPSTAn. 0 = not detect Transfer Ready Flag (REDY) [0] 1 = multi master error detect 1 This bit indicates that SPTDATn or SPRDATn is ready to transmit or receive. This flag is automatically cleared by writing data to SPTDATn. 0 = not ready 1 = data Tx/Rx ready 0 R/W R R Description SPI channel 0 status register SPI channel 1 status register Description Reset Value 0x01 0x01 Initial State
22-7
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
SPI
S3C2440X RISC MICROPROCESSOR
SPI PIN CONTROL REGISTER When the SPI system is enabled, the direction of pins, except nSS pin, is controlled by MSTR bit of SPCONn register. The direction of nSS pin is always input. When the SPI is a master, nSS pin is used to check multi-master error, provided the SPPIN's ENMUL bit is active, and another GPIO should be used to select a slave. If the SPI is configured as a slave, the nSS pin is used to select SPI as a slave by one master. Register SPPIN0 SPPIN1 SPPINn Reserved Multi Master error detect Enable (ENMUL) Reserved Master Out Keep (KEEP) Address 0x59000008 0x59000028 Bit [7:3] [2] The /SS pin is used as an input to detect multi master error when the SPI system is a master. 0 = disable (general purpose) [1] [0] This bit should be `1'. Determine MOSI drive or release when 1byte transmit is completed (only master). 0 = release 1 = drive the previous level 1 = multi master error detect enable 1 0 0 R/W R/W R/W Description SPI channel 0 pin control register SPI channel 1 pin control register Description Reset Value 0x02 0x02 Initial State
The SPIMISO (MISO) and SPIMOSI (MOSI) data pins are used for transmitting and receiving serial data. When the SPI is configured as a master, SPIMISO (MISO) is the master data input line, SPIMOSI (MOSI) is the master data output line, and SPICLK (SCK) is the clock output line. When the SPI becomes a slave, these pins perform reversed roles. In a multiple-master system, SPICLK (SCK) pins, SPIMOSI (MOSI) pins, and SPIMISO (MISO) pins are tied to configure a group respectively. A master SPI can experience a multi master error, when other SPI device working as a master selects the S3C2410 SPI as a slave. When this error is detected, the following actions are taken immediately. But you must previously set SPPINn's ENMUL bit if you want to detect this error. 1. The SPCONn's MSTR bit is forced to 0 to operate slave mode. 2. The SPSTAn's MULF flag is set, and an SPI interrupt is generated.
22-8
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
SPI
SPI Baud Rate Prescaler Register Register SPPRE0 SPPRE1 SPPREn Prescaler Value Address 0x5900000C 0x5900002C Bit [7:0] R/W R/W R/W Description SPI cannel 0 baud rate prescaler register SPI cannel 1 baud rate prescaler register Description Determine SPI clock rate as above equation. Reset Value 0x00 0x00 Initial State 0x00
Baud rate = PCLK / 2 / (Prescaler value + 1) Note: Baud rate should be less than 25MHz.
SPI Tx Data Register Register SPTDAT0 SPTDAT1 SPTDATn Tx Data Register Address 0x59000010 0x59000030 Bit [7:0] R/W R/W R/W Description SPI channel 0 Tx data register SPI channel 1 Tx data register Description This field contains the data to be transmitted over the SPI channel. Reset Value 0x00 0x00 Initial State 0x00
SPI Rx Data Register Register SPRDAT0 SPRDAT1 SPRDATn Rx Data Register Address 0x59000014 0x59000034 Bit [7:0] R/W R R Description SPI channel 0 Rx data register SPI channel 1 Rx data register Description This field contains the data to be received over the SPI channel. Reset Value 0x00 0x00 Initial State 0x00
22-9
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
CAMERA INTERFACE
CAMERA INTERFACE
OVERVIEW
This specification defines the interface of camera. The camera interface within S3C2440X consists of three parts. The one is the logic of catching camera input signals. The second one is the logic of format conversion and down scaling. And, the last one is the dedicated DMA part. The camera interface supports ITU BT.601/656 8-bit mode. The scaler of camera interface can scale down from below XGA(up to horizontal 1016 pixels) input image into SVGA, VGA, QVGA, CIF, QCIF and any other smaller sizes. Two master ports can be used variable applications like DSC, JPEG, MPEG self image and so on. Camera interface can generate self test patterns as color bar, square box. It could be used in the calibration of image sync signals. Also, video sync signals and pixel clock polarity can be inverted in camera interface by register setting.
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Figure 23-1. Camera interface overview
FEATURES -- Supports ITU-R BT.601/656 (4:2:2 YcbCr 8-bit mode). -- Image down scaling capability for variable applications. -- Two master port for dedicated DMA operation. -- Programmable the polarity of video sync signals. -- Wide horizontal line buffer (Maximum 1016 pixels). -- Format conversion from YCbCr 4:2:2 to YCbCr 4:2:0 -- Programmable burst length for DMA operation.
23-1
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
CAMERA INTERFACE
S3C2440X RISC MICROPROCESSOR
EXTERNAL INTERFACE
Camera interface in S3C2440X can support next ITU video standard. -- ITU BT.601 YCbCr 8-bit mode -- ITU BT.656 YCbCr 8-bit mode SIGNAL DESCRIPTION Name PCLK VSYNC HREF DATA[7:0] CAMCLK I/O I I I I O
1)
Active H H -
Description Pixel Clock, driven by the Camera processor Vertical Sync, driven by the Camera processor Horizontal Sync, driven by the Camera processor Pixel Data for YCbCr, driven by the Camera processor Master Clock to the Camera processor
CAMRST O H Software Reset to the Camera processor Note 1) I/O direction is on the AP side. I : input, O : output, B : bi-direction Table 23-1. Camera interface signal description
TIMING DIAGRAM
1 Frame VSYNC Vertical lines HREF
HREF (1H)
Horizontal width
PCLK Y Cb Y Cr Y Cb Y Cb Y Cr
DATA[7:0]
Figure 23-2. ITU-R BT.601 Input timing diagram
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
CAMERA INTERFACE
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Figure 23-3. ITU-R BT.656 Input timing diagram
There are two timing reference signals in ITU-R BT.656 format, one at the beginning of each vedio data block (start of active video, SAV) and one at the end of each video data block(end of active video, EAV) as shown in Figure 23-3 and Table 23-2.
Data bit number 9 (MSB) 8 7 6 5 4 3 2 1 (Note 1) 0
First word (FF) 1 1 1 1 1 1 1 1 1 1
Second word (00) 0 0 0 0 0 0 0 0 0 0
Third word (00) 0 0 0 0 0 0 0 0 0 0
Forth word (XY) 1 F V H P3 P2 P1 P0 0 0
Note 1) For compatibility with existing 8-bit interfaces, the values of bits D1 and D0 are not defined. F = 0 (during field 1), 1 (during field 2) V = 0 (elsewhere), 1 (during field blanking) H = 0 (in SAV : Start of Active Video), 1 (in EAV : End of Active Video) P0, P1, P2, P3 = protection bit Table 23-2. Video timing reference codes of ITU-R BT.656 format Camera interface logic can catch the video sync bits like H(SAV,EAV) and V(Frame Sync) after reserved data as "FF-00-00".
23-3
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
CAMERA INTERFACE
S3C2440X RISC MICROPROCESSOR
CAMERA INTERFACE OPERATION
TWO DMA PORTS CAMIF has two DMA port. A-port and B-port are separated each other. At view of system bus, two ports are independent. The A-port stores the scale-downed and format-converted image to A-port ping-pong memories. The B-port stores the only format-converted image to B-port ping-pong memories. These two master ports enable variable application like DSC (Digital Steel Camera), MPEG self image, etc. For example, A-port image can be used as preview image, and B-port image can be used as JPEG image in DSC application. Also, A-port or B-port can be separately disabled.
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Figure 23-4. Two DMA ports
23-4
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
CAMERA INTERFACE
CLOCK DOMAIN CAMIF has three clock domains. The one is the system bus clock, which is HCLK. Another is the pixel clock, which is PCLK. And, the other is the camera interface operation clock, which is OP_CLOCK. The system clock must be faster than any other clock. And, the pixel clock must be double speed compared to the operation clock of camera interface. As shown in figure 1-6, CAMCLK must be divided from the fixed frequency like USB PLL clock. OP_CLOCK has the half frequency of CAMCLK.
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Figure 23-5. CAMIF clock generation
23-5
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
CAMERA INTERFACE
S3C2440X RISC MICROPROCESSOR
FRAME MEMORY HIRERARCHY Frame memories consist of 4 ping-pong memories for each A- and B-ports. Each ping-pong memory has three elements memory that is luminance, chrominance Cb, and chrominance Cr. After getting the input of ITU format, CAMIF transfers output data to AHB-bus for memory access. It is recommended that the arbitration priority of CAMIF must be higher than other master except display controller. If AHB-bus is traffic enough that DMA operation is not ending during one horizontal sync signal, it will enter into mal-function. So, the priority of CAMIF must be separated to other round-robin priorities.
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Figure 23-6. Ping-pong memory hierarchy
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Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
CAMERA INTERFACE
MEMORY STORING METHOD The storing method to the frame memories is the little-endian method. The first entering pixels stored into LSB sides, and the last entering pixels stored into MSB sides. The carried data by AHB bus is 32-bit word. So, CAMIF make the each Y-Cb-Cr words by little endian style. Rightly, the carried data is the format-converted or scaled and format-converted data.
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Figure 23-7. Memory storing style
23-7
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
CAMERA INTERFACE
S3C2440X RISC MICROPROCESSOR
TIMING DIAGRAM FOR REGISTER SETTING The first register setting for frame capture command can be occurred anytime in operation. For capturing fully occupied frame, the next frame must be captured. And, for another capture, you can program the second register setting in interrupt service routine. Be sure that interrupt is flagged on the start of the captured frame period. One pulse interrupt signal can be programmed by IRQFREE of CTRL register as "1".
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Figure 23-8. Timing diagram for register setting
23-8
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
CAMERA INTERFACE
SOFTWARE INTERFACE
This Camera interface provides a generic data-exchange method. But, you should keep in mind that write registers and read registers are separated. A-port sends scaled output to the AHB bus as in Figure 23-1. B-port sends only format conversion or scaled output to the AHB bus. There is 4 Ping-Pong memories. Consequently, 4 sets of YCb-Cr addresses exist.
CAMERA INTERFACE SPECIAL REGISTERS 1. WRITE REGISTER
A IMAGE SIZE REGISTER Register Address R/W W Description A-port Image Size Reset Value 0xc8258
ASIZE 0x4F000000 NOTE) The Base address is TBD ASIZE AHSIZE Bit [19:10]
Description These bits indicate the horizontal pixel number of the target image for A-port. If target image size is QCIF, these bits should be 10'd176, that is 10'hb0. These bits indicate the vertical pixel number of the target image for A-port. If target image size is QCIF, these bits should be 10'd144, that is 10'h90.
Initial State 0x320
AVSIZE
[9:0]
0x258
A Y1 START ADDRESS REGISTER Register STAY1 Address 0x4F000004 R/W R/W Description
A-port Image 1st ping-pong memory
Reset Value 0xc073f000
Y start address
STAY1 STAY1
Bit [31:0]
Description This register value will be the start address of luminance for 1 Ping-Pong memory of A-port
st
Initial State 0xc073f000
23-9
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
CAMERA INTERFACE
S3C2440X RISC MICROPROCESSOR
A Y2 START ADDRESS REGISTER Register STAY2 Address 0x4F000008 R/W R/W Description
A-port Image 2nd ping-pong memory Y start address
Reset Value 0xc07eec80
STAY2 STAY2
Bit [31:0]
Description This register value will be the start address of luminance for 2 Ping-Pong memory of A-port
nd
Initial State 0xc07eec80
A Y3 START ADDRESS REGISTER Register STAY3 Address 0x4F00000C R/W R/W Description
A-port Image 3rd ping-pong memory Y start address
Reset Value 0xc089e900
STAY3 STAY3
Bit [31:0]
Description This register value will be the start address of luminance for 3 Ping-Pong memory of A-port
rd
Initial State 0xc089e900
A Y4 START ADDRESS REGISTER Register STAY4 Address 0x4F000010 R/W R/W Description
A-port Image 4th ping-pong memory Y start address
Reset Value 0xc094e580
STAY4 STAY4
Bit [31:0]
Description This register value will be the start address of luminance for 4 Ping-Pong memory of A-port
th
Initial State 0xc094e580
23-10
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
CAMERA INTERFACE
A Y BURST REGISTER Register AYBURST Address 0x4F000014 R/W W Description
A-port Image Y data burst length
Reset Value 0x00000000
AYBURST AYBURST1 AYBURST2
Bit [31:16] [15:0]
Description These bits indicate main burst length of A-port during the memory read/write access for luminance data.
Initial State 0x0000
These bits indicate remained burst length of A-port during the memory read/write access for luminance data. * In CIF case, AYBURST1=8, AYBURST2=8 are recommended.
0x0000
Example 1. Target image size : QCIF (horizontal Y width = 176 pixels. 1 pixel = 1 Byte. 1 word = 4 pixel) 176 / 4 = 44 word. 44 % 8 = 4 main burst = 8, remained burst = 4 Example 2. Target image size : VGA (horizontal Y width = 640 pixels. 1 pixel = 1 Byte. 1 word = 4 pixel) 640 / 4 = 160 word. 160 % 16 = 0 main burst = 16, remained burst = 16
A CB BURST REGISTER Register ACBBURST Address 0x4F000018 R/W W Description
A-port Image Cb data burst length
Reset Value 0x00000000
ACBBURST ACBBURST1 ACBBURST2
Bit [31:16] [15:0]
Description These bits indicate main burst length of A-port during the memory read/write access for Chrominance Cb data.
Initial State 0x0000 0x0000
These bits indicate remained burst length of A-port during the memory read/write access for Chrominance Cb data. * In CIF case, ACBBURST1=4, ACBBURST2=4 are recommended. Example 1. Target image size : QCIF (horizontal C width = 88 pixels. 1 pixel = 1 Byte. 1 word = 4 pixel) 88 / 4 = 22 word. 22 % 4 = 2 main burst = 4, remained burst = 2 (internally two single operations)
Example 2. Target image size : VGA (horizontal C width = 320 pixels. 1 pixel = 1 Byte. 1 word = 4 pixel) 320 / 4 = 80 word. 80 % 16 = 0 main burst = 16, remained burst = 16
23-11
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
CAMERA INTERFACE
S3C2440X RISC MICROPROCESSOR
A CR BURST REGISTER Register ACRBURST Address 0x4F00001C R/W W Description
A-port Image Cr data burst length
Reset Value 0x00000000
ACRBURST ACRBURST1 ACRBURST2
Bit [31:16] [15:0]
Description These bits indicate main burst length of A-port during the memory read/write access for Chrominance Cr data.
Initial State 0x0000 0x0000
These bits indicate remained burst length of A-port during the memory read/write access for Chrominance Cr data. * In CIF case, ACRBURST1=4, ACRBURST2=4 are recommended. Example 1. Target image size : QCIF (horizontal C width = 88 pixels. 1 pixel = 1 Byte. 1 word = 4 pixel) 88 / 4 = 22 word. 22 % 4 = 2 main burst = 4, remained burst = 2 (internally two single operations)
Example 2. Target image size : VGA (horizontal C width = 320 pixels. 1 pixel = 1 Byte. 1 word = 4 pixel) 320 / 4 = 80 word. 80 % 16 = 0 main burst = 16, remained burst = 16
23-12
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
CAMERA INTERFACE
B IMAGE SIZE REGISTER Register BSIZE Address 0x4F000020 R/W W Description B-port Image Size Reset Value 0xc8258
ASIZE BHSIZE
Bit [19:10]
Description These bits indicate the horizontal pixel number of the target image for B-port. If target image size is QCIF, these bits should be 10'd176, that is 10'hb0. These bits indicate the vertical pixel number of the target image for B-port. If target image size is QCIF, these bits should be 10'd144, that is 10'h90.
Initial State 0x320
BVSIZE
[9:0]
0x258
B Y1 START ADDRESS REGISTER Register STBY1 Address 0x4F000024 R/W W Description
B-port Image 1st ping-pong memory Y start address
Reset Value 0xc073f000
STBY1 STBY1
Bit [31:0]
Description This register value will be the start address of luminance for 1 Ping-Pong memory of B-port
st
Initial State 0xc073f000
B Y2 START ADDRESS REGISTER Register STBY2 Address 0x4F000028 R/W W Description
B-port Image 2nd ping-pong memory Y start address
Reset Value 0xc07eec80
STBY2 STBY2
Bit [31:0]
Description This register value will be the start address of luminance for 2 Ping-Pong memory of B-port
nd
Initial State 0xc07eec80
23-13
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
CAMERA INTERFACE
S3C2440X RISC MICROPROCESSOR
B Y3 START ADDRESS REGISTER Register STBY3 Address 0x4F00002C R/W W Description
B-port Image 3rd ping-pong memory Y start address
Reset Value 0xc089e900
STBY3 STBY3
Bit [31:0]
Description This register value will be the start address of luminance for 3 Ping-Pong memory of B-port
rd
Initial State 0xc089e900
B Y4 START ADDRESS REGISTER Register STBY4 Address 0x4F000030 R/W W Description
B-port Image 4th ping-pong memory Y start address
Reset Value 0xc094e580
STBY4 STBY4
Bit [31:0]
Description This register value will be the start address of luminance for 4 Ping-Pong memory of B-port
th
Initial State 0xc094e580
B Y BURST REGISTER Register BYBURST Address 0x4F000034 R/W W Description
B-port Image Y data burst length
Reset Value 0x00000000
BYBURST BYBURST1 BYBURST2
Bit [31:16] [15:0]
Description These bits indicate main burst length of B-port during the memory read/write access for luminance data.
Initial State 0x0000
These bits indicate remained burst length of B-port during the memory read/write access for luminance data. * In CIF case, BYBURST1=8, BYBURST2=8 are recommended.
0x0000
Example 1. Target image size : QCIF (horizontal Y width = 176 pixels. 1 pixel = 1 Byte. 1 word = 4 pixel) 176 / 4 = 44 word. 44 % 8 = 4 main burst = 8, remained burst = 4 Example 2. Target image size : VGA (horizontal Y width = 640 pixels. 1 pixel = 1 Byte. 1 word = 4 pixel) 640 / 4 = 160 word. 160 % 16 = 0 main burst = 16, remained burst = 16
23-14
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
CAMERA INTERFACE
B CB BURST REGISTER Register BCBBURST Address 0x4F000038 R/W W Description
B-port Image Cb data burst length
Reset Value 0x00000000
BCBBURST BCBBURST1 BCBBURST2
Bit [31:16] [15:0]
Description These bits indicate main burst length of B-port during the memory read/write access for Chrominance Cb data.
Initial State 0x0000 0x0000
These bits indicate remained burst length of B-port during the memory read/write access for Chrominance Cb data. * In CIF case, BCBBURST1=4, BCBBURST2=4 are recommended. Example 1. Target image size : QCIF (horizontal C width = 88 pixels. 1 pixel = 1 Byte. 1 word = 4 pixel) 88 / 4 = 22 word. 22 % 4 = 2 main burst = 4, remained burst = 2 (internally two single operations) Example 2. Target image size : VGA (horizontal C width = 320 pixels. 1 pixel = 1 Byte. 1 word = 4 pixel) 320 / 4 = 80 word. 80 % 16 = 0 main burst = 16, remained burst = 16
B CR BURST REGISTER Register BCRBURST Address 0x4F00003C R/W W Description
B-port Image Cr data burst length
Reset Value 0x00000000
BCRBURST BCRBURST1 BCRBURST2
Bit [31:16] [15:0]
Description These bits indicate main burst length of B-port during the memory read/write access for Chrominance Cr data.
Initial State 0x0000 0x0000
These bits indicate remained burst length of B-port during the memory read/write access for Chrominance Cr data. * In CIF case, BCRBURST1=4, BCRBURST2=4 are recommended. Example 1. Target image size : QCIF (horizontal C width = 88 pixels. 1 pixel = 1 Byte. 1 word = 4 pixel) 88 / 4 = 22 word. 22 % 4 = 2 main burst = 4, remained burst = 2 (internally two single operations) Example 2. Target image size : VGA (horizontal C width = 320 pixels. 1 pixel = 1 Byte. 1 word = 4 pixel) 320 / 4 = 80 word. 80 % 16 = 0 main burst = 16, remained burst = 16
23-15
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
CAMERA INTERFACE
S3C2440X RISC MICROPROCESSOR
A LAST HREF DISTANCE WIDTH REGISTER Register ADISTWIDTH Address 0x4F000040 R/W W Description
A-port distance and width for last hsync generation
Reset Value 0x1b581040
ADISTWIDTH ADIST
Bit [31:16]
Description These bits indicate the distance from the start of external last HREF to the start of imitative HREF for last DMA operation for Aport. ADIST = (Tpclk/Tsys) x 1.5 x H x 2 (Tpclk : the period of incoming pixel clock, Tsys : the period of system clock, H : the horizontal pixel number of source image) If you do not view the last horizontal line in your display, you should increase the number of ADIST by sufficient values. If it is not effective, contact the developer in samsung, please.
Initial State 0x1b58
AWIDTH
[15:0]
These bits indicate the width of imitative HREF for last DMA operation for A-port. AWIDTH = (Tpclk/Tsys) x 1.5 x H x 2 (Tpclk : the period of incoming pixel clock, Tsys : the period of system clock, H : the horizontal pixel number of source image) If you do not view the last horizontal line in your display, you should increase the number of ADIST by sufficient values. If it is not effective, contact the developer in samsung, please. 0x1040
Example 1. Source image size : VGA (640 x 480), Tpclk : 74ns (13.5MHz), Tsys : 10ns (100MHz) ADIST = (74/10) x 1.5 x 640 x 2 = 14208 AWIDTH = (74/10) x 1.5 x 640 x 2 = 14208
23-16
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
CAMERA INTERFACE
B LAST HREF DISTANCE WIDTH REGISTER Register BDISTWIDTH Address 0x4F000044 R/W W Description
B-port distance and width for last hsync generation
Reset Value 0x1b581040
ADISTWIDTH BDIST
Bit [31:16]
Description These bits indicate the distance from the start of external last HREF to the start of imitative HREF for last DMA operation for Bport. BDIST = (Tpclk/Tsys) x 1.5 x H x 2 (Tpclk : the period of incoming pixel clock, Tsys : the period of system clock, H : the horizontal pixel number of source image) If you do not view the last horizontal line in your display, you should increase the number of BDIST by sufficient values. If it is not effective, contact the developer in samsung, please.
Initial State 0x1b58
BWIDTH
[15:0]
These bits indicate the width of imitative HREF for last DMA operation for B-port. BWIDTH = (Tpclk/Tsys) x 1.5 x H x 2 (Tpclk : the period of incoming pixel clock, Tsys : the period of system clock, H : the horizontal pixel number of source image) If you do not view the last horizontal line in your display, you should increase the number of BDIST by sufficient values. If it is not effective, contact the developer in samsung, please. 0x1040
Example 1. Source image size : VGA (640 x 480), Tpclk : 74ns (13.5MHz), Tsys : 10ns (100MHz) BDIST = (74/10) x 1.5 x 640 x 2 = 14208 BWIDTH = (74/10) x 1.5 x 640 x 2 = 14208
23-17
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
CAMERA INTERFACE
S3C2440X RISC MICROPROCESSOR
Y SCALE RATIO REGISTER Register YRATIO Address 0x4F00004C R/W W Description
A-port scaling ratio for luminace
Reset Value 0x14001400
YRATIO YHRATIO YVRATIO
Bit [31:16] [15:0]
Description
(Source Y size / Target Y size) x 4096 (Source Y size / Target Y size) x 4096
Initial State 0x1400 0x1400
Example 1. Source image Y size : VGA (640 x 480), Target image Y size for A-port : QCIF (176 x 144) YHRATIO = (640 / 176) x 4096 = 14894.545 14894 (in round numbers) : 0x3a2e YVRATIO = (480 / 144) x 4096 = 13653.333 13653 (in round numbers) : 0x3555
C SCALE RATIO REGISTER Register CRATIO Address 0x4F000050 R/W W Description
A-port scaling ratio for chrominace
Reset Value 0x14002800
CRATIO CHRATIO CVRATIO
Bit [31:16] [15:0]
Description
(Source C size / Target C size) x 4096 (Source C size / Target C size) x 4096
Initial State 0x1400 0x2800
Example 1. Source image C size : VGA (320 x 480), Target image C size for A-port : QCIF (88 x 72) CHRATIO = (320 / 88) x 4096 = 14894.545 14894 (in round numbers) : 0x3a2e CVRATIO = (480 / 72) x 4096 = 27306.666 27306 (in round numbers) : 0x6aaa
23-18
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
CAMERA INTERFACE
Y ORIGINAL SIZE REGISTER Register YORIGINAL Address 0x4F000054 R/W W
Y original size
Description
Reset Value 0xc8258
YORIGINAL YORIGINALX
Bit [25:16]
Description These bits indicate the Y horizontal size of source image. If input size is VGA (640 x 480), YORIGINALX should be 640.
Initial State 0x320
YORIGINALY
[9:0]
These bits indicate the Y vertical size of source image. If input size is VGA (640 x 480), YORIGINALY should be 480. 0x258
C ORIGINAL SIZE REGISTER Register CORIGINAL Address 0x4F00005C R/W W
C original size
Description
Reset Value 0x64258
YORIGINAL CORIGINALX
Bit [25:16]
Description These bits indicate the C horizontal size of source image. If input size is VGA (640 x 480), CORIGINALX should be 320.
Initial State 0x190
CORIGINALY
[9:0]
These bits indicate the C vertical size of source image. If input size is VGA (640 x 480), CORIGINALY should be 480. 0x258
A CB1 START ADDRESS REGISTER Register STACB1 Address 0x4F000074 R/W W Description
A-port Image 1st ping-pong memory Cb start address
Reset Value 0xc073f000
STACB1 STACB1
Bit [31:0]
Description This register value will be the start address of Chrominace Cb for 1st Ping-Pong memory of A-port
Initial State 0xc073f000
23-19
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
CAMERA INTERFACE
S3C2440X RISC MICROPROCESSOR
A CB2 START ADDRESS REGISTER Register STACB2 Address 0x4F000078 R/W W Description
A-port Image 2nd ping-pong memory Cb start address
Reset Value 0xc07eec80
STACB2 STACB2
Bit [31:0]
Description This register value will be the start address of Chrominace Cb for nd 2 Ping-Pong memory of A-port
Initial State 0xc07eec80
A CB3 START ADDRESS REGISTER Register STACB3 Address 0x4F00007C R/W W Description
A-port Image 3rd ping-pong memory Cb start address
Reset Value 0xc089e900
STACB3 STACB3
Bit [31:0]
Description This register value will be the start address of Chrominace Cb for rd 3 Ping-Pong memory of A-port
Initial State 0xc089e900
A CB4 START ADDRESS REGISTER Register STACB4 Address 0x4F000080 R/W W Description
A-port Image 4th ping-pong memory Cb start address
Reset Value 0xc094e580
STACB4 STACB4
Bit [31:0]
Description This register value will be the start address of Chrominace Cb for th 4 Ping-Pong memory of A-port
Initial State 0xc094e580
23-20
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
CAMERA INTERFACE
A CR1 START ADDRESS REGISTER Register STACR1 Address 0x4F000084 R/W W Description
A-port Image 1st ping-pong memory Cr start address
Reset Value 0xc073f000
STACR1 STACR1
Bit [31:0]
Description This register value will be the start address of Chrominace Cr for st 1 Ping-Pong memory of A-port
Initial State 0xc073f000
A CR2 START ADDRESS REGISTER Register STACR2 Address 0x4F000088 R/W W Description
A-port Image 2nd ping-pong memory Cr start address
Reset Value 0xc07eec80
STACR2 STACR2
Bit [31:0]
Description This register value will be the start address of Chrominace Cr for nd 2 Ping-Pong memory of A-port
Initial State 0xc07eec80
A CR3 START ADDRESS REGISTER Register STACR3 Address 0x4F00008C R/W W Description
A-port Image 3rd ping-pong memory Cr start address
Reset Value 0xc089e900
STACR3 STACR3
Bit [31:0]
Description This register value will be the start address of Chrominace Cr for rd 3 Ping-Pong memory of A-port
Initial State 0xc089e900
23-21
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
CAMERA INTERFACE
S3C2440X RISC MICROPROCESSOR
A CR4 START ADDRESS REGISTER Register STACR4 Address 0x4F000090 R/W W Description
A-port Image 4th ping-pong memory Cr start address
Reset Value 0xc094e580
STACR4 STACR4
Bit [31:0]
Description This register value will be the start address of Chrominace Cr for th 4 Ping-Pong memory of A-port
Initial State 0xc094e580
B CB1 START ADDRESS REGISTER Register STBCB1 Address 0x4F00009C R/W W Description
B-port Image 1st ping-pong memory Cb start address
Reset Value 0xc073f000
STBCB1 STBCB1
Bit [31:0]
Description This register value will be the start address of Chrominace Cb for st 1 Ping-Pong memory of B-port
Initial State 0xc073f000
B CB2 START ADDRESS REGISTER Register STBCB2 Address 0x4F0000A0 R/W W Description
B-port Image 2nd ping-pong memory Cb start address
Reset Value 0xc07eec80
STBCB2 STBCB2
Bit [31:0]
Description This register value will be the start address of Chrominace Cb for nd Ping-Pong memory of B-port 2
Initial State 0xc07eec80
23-22
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
CAMERA INTERFACE
B CB3 START ADDRESS REGISTER Register STBCB3 Address 0x4F0000A4 R/W W Description
B-port Image 3rd ping-pong memory Cb start address
Reset Value 0xc089e900
STBCB3 STBCB3
Bit [31:0]
Description This register value will be the start address of Chrominace Cb for rd 3 Ping-Pong memory of B-port
Initial State 0xc089e900
B CB4 START ADDRESS REGISTER Register STBCB4 Address 0x4F0000A8 R/W W Description
B-port Image 4th ping-pong memory Cb start address
Reset Value 0xc094e580
STBCB4 STBCB4
Bit [31:0]
Description This register value will be the start address of Chrominace Cb for th 4 Ping-Pong memory of B-port
Initial State 0xc094e580
B CR1 START ADDRESS REGISTER Register STBCR1 Address 0x4F0000AC R/W W Description
B-port Image 1st ping-pong memory Cr start address
Reset Value 0xc073f000
STBCR1 STBCR1
Bit [31:0]
Description This register value will be the start address of Chrominace Cr for st 1 Ping-Pong memory of B-port
Initial State 0xc073f000
B CR2 START ADDRESS REGISTER Register STBCR2 Address 0x4F0000B0 R/W W Description
B-port Image 2nd ping-pong memory Cr start address
Reset Value 0xc07eec80
STBCR2 STBCR2
Bit [31:0]
Description This register value will be the start address of Chrominace Cr for nd 2 Ping-Pong memory of B-port
Initial State 0xc07eec80
23-23
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
CAMERA INTERFACE
S3C2440X RISC MICROPROCESSOR
B CR3 START ADDRESS REGISTER Register STBCR3 Address 0x4F0000B4 R/W W Description
B-port Image 3rd ping-pong memory Cr start address
Reset Value 0xc089e900
STBCR3 STBCR3
Bit [31:0]
Description This register value will be the start address of Chrominace Cr for rd 3 Ping-Pong memory of B-port
Initial State 0xc089e900
B CR4 START ADDRESS REGISTER Register STBCR4 Address 0x4F0000B8 R/W W Description
B-port Image 4th ping-pong memory Cr start address
Reset Value 0xc094e580
STBCR4 STBCR4
Bit [31:0]
Description This register value will be the start address of Chrominace Cr for th 4 Ping-Pong memory of B-port
Initial State 0xc094e580
23-24
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
CAMERA INTERFACE
CONTROL REGISTER Register CTRL CTRL SOFTRST Address 0x4F0000BC Bit [30] 1 = software reset 0 = normal ABSAME BENAS [29] [20] This bit indicates which is same both A-port image and B-port image. If this bit is 1, A/B-port image will be the scaled images. This bit indicates the controllability of burst length for DMA operations. 1 = software gives burst length 0 = self burst length generation CAMRST [19] This bit indicates the software reset of external camera processor. 1 = software reset for camera processor 0 = normal IMGCAPA IRQFREE [18] [17] This bit indicates the image capture enable for A-port. If this bit set to 1, one clock pulse will be internally generated. This bit can clear the interrupt of camera interface. 1 = Interrupt clear 0 = normal TESTPT [16:14] These bits indicate the test pattern for verifying the incoming ITU-R BT.601/656 sync signals and fundamental operations. 000 = bypass (external input) 001 = color-bar pattern 010 = square-box pattern 011 = solid-line pattern 100 = check pattern 101 = horizontal increasing pattern 110 = DC pattern 111 = reserved. SWAPYUV [13] This bit controls the swap between Y and UV sequence. 1 = UYVY 0 = YUYV (recommended) YUVORD UVOFFSET [12] [11] This bit indicates Y/UV order. It is recommended to fix 0. This bit indicates the data offset of UV signals. 1 = offset binary 0 = normal (recommended) 0 0 0 000 0 0 0 0 0 R/W W Description
Camera interface control
Reset Value 0x00000000 Initial State 0
Description This bit indicates software reset of camera interface.
23-25
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
CAMERA INTERFACE
S3C2440X RISC MICROPROCESSOR
HSYNCPOL
[9]
This bit indicates the polarity of incoming horizontal sync signal. 1 = inversion (low active) 0 = normal (high active)
0
VSYNCPOL
[8]
This bit indicates the polarity of incoming vertical sync signal. 1 = inversion (low active) 0 = normal (high active)
0
PCLKPOL
[7]
This bit indicates the polarity of incoming pixel clock signal. 1 = inversion (for not sufficient setup/hold timing) 0 = normal (recommended)
0
IMGFMT
[6]
This bit indicates the format of input interface. 1 = ITU-R BT.601 YCbCr 4:2:2 8-bit mode 0 = ITU-R BT.656 YCbCr 4:2:2 8-bit mode
0
IMGCAPB
[2]
This bit indicates the image capture enable for B-port. If this bit set to 1, one clock pulse will be internally generated.
0
23-26
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
CAMERA INTERFACE
2. READ REGISTER
STATUS READ REGISTER Register RDSTAT RDSTAT Reserved RDFCNTA Address 0x4F000000 Bit [31:30] [29:28] These bits indicate the count of 4 Ping-Pong frame memories for A-port. 00 = A-port 1 frame
nd 01 = A-port 2 frame st
R/W R
Description
Camera interface status for CPU read
Reset Value 0x00000000 Initial State 00 00
Description
10 = A-port 3 frame 11 = A-port 4 frame RDFCNTB [27:26] These bits indicate the count of 4 Ping-Pong frame memories for B-port. 00 = B-port 1 frame
nd 01 = B-port 2 frame st th
rd
00
10 = B-port 3 frame 11 = B-port 4 frame RDCAMRST RDIMGCAPA [19] [18] This bit indicates the software reset of external camera processor. This bit indicates the enable state of A-port image capture sync to VSYNC signal. If capture is enabled, this bit will remain high to VYNC falling edge. This bit indicates the state of interrupt free. 1 = Interrupt clear 0 = normal RDTESTPT [16:14] These bits indicate the test pattern for verifying the incoming ITU-R BT.601/656 sync signals and fundamental operations. 000 = bypass (external input) 001 = color-bar pattern 010 = square-box pattern 011 = solid-line pattern 100 = check pattern 101 = horizontal increasing pattern 110 = DC pattern 111 = reserved. RDSWAPYUV [13] This bit indicates the swap between Y and UV sequence. 1 = UYVY 0 = YUYV (recommended) 0 000 0 0
th
rd
RDIRQFREE
[17]
0
23-27
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
CAMERA INTERFACE
S3C2440X RISC MICROPROCESSOR
RDYUVORD RDUVOFFSET
[12] [11]
This bit indicates Y/UV order. It is recommended to fix 0. This bit indicates the data offset of UV signals. 1 = offset binary 0 = normal (recommended)
0 0
RDHSYNCPOL
[9]
This bit indicates the polarity of incoming horizontal sync signal. 1 = inversion (low active) 0 = normal (high active)
0
RDVSYNCPOL
[8]
This bit indicates the polarity of incoming vertical sync signal. 1 = inversion (low active) 0 = normal (high active)
0
RDPCLKPOL
[7]
This bit indicates the polarity of incoming pixel clock signal. 1 = inversion (for not sufficient setup/hold timing) 0 = normal (recommended)
0
RDIMGFMT
[6]
This bit indicates the format of input interface. 1 = ITU-R BT.601 YCbCr 4:2:2 8-bit mode 0 = ITU-R BT.656 YCbCr 4:2:2 8-bit mode
0
23-28
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
CAMERA INTERFACE
A Y START ADDRESS READ REGISTER Register RDSTAY Address 0x4F000014 R/W R Description
A-port Image current Y start address
Reset Value 0x00000000
RDSTAY RDSTAY
Bit [31:0]
Description
Initial State
This register value indicates the current start address of luminance 0x00000000 for A-port
A CB START ADDRESS READ REGISTER Register RDSTACB Address 0x4F000018 R/W R Description
A-port Image current Cb start address
Reset Value 0x00000000
RDSTACB RDSTACB
Bit [31:0]
Description This register value indicates the current start address of Chrominance Cb for A-port
Initial State 0x00000000
A CR START ADDRESS READ REGISTER Register RDSTACR Address 0x4F00001C R/W R Description
A-port Image current Cr start address
Reset Value 0x00000000
RDSTACR RDSTACR
Bit [31:0]
Description This register value indicates the current start address of Chrominance Cr for A-port
Initial State 0x00000000
A CB1 START ADDRESS READ REGISTER Register RDSTACB1 Address 0x4F000020 R/W R Description
A-port Image 1st ping-pong memory Cb start address
Reset Value 0xc073f000
RDSTACB1 RDSTACB1
Bit [31:0]
Description This register value indicates the start address of Chrominance Cb st for 1 Ping-Pong memory of A-port
Initial State 0xc073f000
23-29
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
CAMERA INTERFACE
S3C2440X RISC MICROPROCESSOR
A CR1 START ADDRESS READ REGISTER Register RDSTACR1 Address 0x4F000024 R/W R Description
A-port Image 1st ping-pong memory Cr start address
Reset Value 0xc073f000
RDSTACR1 RDSTACR1
Bit [31:0]
Description This register value indicates the start address of Chrominance Cr st for 1 Ping-Pong memory of A-port
Initial State 0xc073f000
B Y1 START ADDRESS READ REGISTER Register RDSTBY1 Address 0x4F000028 R/W R Description
B-port Image 1st ping-pong memory Y start address
Reset Value 0xc073f000
RDSTBY1 RDSTBY1
Bit [31:0]
Description This register value indicates the start address of luminance for 1 Ping-Pong memory of B-port
st
Initial State 0xc073f000
B Y2 START ADDRESS READ REGISTER Register RDSTBY2 Address 0x4F00002C R/W R Description
B-port Image 2nd ping-pong memory Y start address
Reset Value 0xc07eec80
RDSTBY2 RDSTBY2
Bit [31:0]
Description his register value indicates the start address of luminance for 2 Ping-Pong memory of B-port
nd
Initial State 0xc07eec80
B Y3 START ADDRESS READ REGISTER Register RDSTBY3 Address 0x4F000030 R/W R Description
B-port Image 3rd ping-pong memory Y start address
Reset Value 0xc089e900
RDSTBY3 RDSTBY3
Bit [31:0]
Description his register value indicates the start address of luminance for 3 Ping-Pong memory of B-port
rd
Initial State 0xc089e900
23-30
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
CAMERA INTERFACE
B Y4 START ADDRESS READ REGISTER Register RDSTBY4 Address 0x4F000034 R/W R Description
B-port Image 4th ping-pong memory Y start address
Reset Value 0xc094e580
RDSTBY4 RDSTBY4
Bit [31:0]
Description his register value indicates the start address of luminance for 4 Ping-Pong memory of B-port
th
Initial State 0xc094e580
B Y START ADDRESS READ REGISTER Register RDSTBY Address 0x4F000038 R/W R Description
B-port Image current Y start address
Reset Value 0x00000000
RDSTBY RDSTBY
Bit [31:0]
Description
Initial State
This register value indicates the current start address of luminance 0x00000000 for B-port
B CB START ADDRESS READ REGISTER Register RDSTBCB Address 0x4F00003C R/W R Description
B-port Image current Cb start address
Reset Value 0x00000000
RDSTBCB RDSTBCB
Bit [31:0]
Description This register value indicates the current start address of chrominance Cb for B-port
Initial State 0x00000000
B CR START ADDRESS READ REGISTER Register RDSTBCR Address 0x4F000040 R/W R Description
B-port Image current Cr start address
Reset Value 0x00000000
RDSTBCR RDSTBCR
Bit [31:0]
Description This register value indicates the current start address of chrominance Cr for B-port
Initial State 0x00000000
23-31
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
CAMERA INTERFACE
S3C2440X RISC MICROPROCESSOR
B CB1 START ADDRESS READ REGISTER Register RDSTBCB1 Address 0x4F000044 R/W R Description
B-port Image 1st ping-pong memory Cb start address
Reset Value 0xc073f000
RDSTBCB1 RDSTBCB1
Bit [31:0]
Description This register value indicates the start address of Chrominance Cb st for 1 Ping-Pong memory of B-port
Initial State 0xc073f000
B CR1 START ADDRESS READ REGISTER Register RDSTBCR1 Address 0x4F000048 R/W R Description
B-port Image 1st ping-pong memory Cr start address
Reset Value 0xc073f000
RDSTBCR1 RDSTBCR1
Bit [31:0]
Description This register value indicates the start address of Chrominance Cr st for 1 Ping-Pong memory of B-port
Initial State 0xc073f000
A LAST HREF DISTANCE WIDTH READ REGISTER Register RDADISTWIDTH Address 0x4F00004C R/W R Description
A-port distance and width for last hsync generation
Reset Value 0x1b581040
RDADISTWIDTH RDADIST
Bit [31:16]
Description These bits indicate the distance from the start of external last HREF to the start of imitative HREF for last DMA operation for Aport. These bits indicate the width of imitative HREF for last DMA operation for A-port.
Initial State 0x1b58
RDAWIDTH
[15:0]
0x1040
23-32
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
CAMERA INTERFACE
B LAST HREF DISTANCE WIDTH READ REGISTER Register RDBDISTWIDTH Address 0x4F000050 R/W R Description
B-port distance and width for last hsync generation
Reset Value 0x1b581040
RDBDISTWIDTH RDBDIST
Bit [31:16]
Description These bits indicate the distance from the start of external last HREF to the start of imitative HREF for last DMA operation for Bport. These bits indicate the width of imitative HREF for last DMA operation for B-port.
Initial State 0x1b58
RDBWIDTH
[15:0]
0x1040
23-33
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
BUS PRIORITIES
BUS PRIORITIES
OVERVIEW
The bus arbitration logic determines the priorities of bus masters. It supports a combination of rotation priority mode and fixed priority mode. BUS PRIORITY MAP The S3C2440X01 holds eleven bus masters including DRAM refresh controller, LCD_DMA, DMA0, DMA1, DMA2, DMA3, USB_HOST_DMA, EXT_BUS_MASTER, Test interface controller (TIC), and ARM920T. The following list shows the priorities among these bus masters after a reset: 1. DRAM refresh controller 2. LCD_DMA 3. DMA0 4. DMA1 5. DMA2 6. DMA3 7. USB host DMA 8. External bus master 9. TIC 10. ARM920T 11. Reserved Among those bus masters, four DMAs operate under the rotation priority, while others run under the fixed priority.
24-1
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
BUS PRIORITIES
S3C2440X RISC MICROPROCESSOR
NOTES
24-2
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X RISC MICROPROCESSOR
ELECTRICAL DATA
25
Parameter DC Supply Voltage DC Input Voltage
ELECTRICAL DATA
ABSOLUTE MAXIMUM RATINGS
Table 25-1. Absolute Maximum Rating Symbol VDDi VDDIO VDDRTC VIN VOUT IIN TSTG 1.2V VDD 3.3V VDD 3.0V VDD 3.3V Input buffer 3.3V Interface / 5V Tolerant input buffer DC Output Voltage DC Input (Latch-up) Current Storage Temperature 3.3V Output buffer 200 - 65 to 150 Rating 1.8 4.8 4.5 4.8 6.5 4.8 mA
o
Unit
V
C
RECOMMENDED OPERATING CONDITIONS
Table 25-2. Recommended Operating Conditions Parameter DC Supply Voltage for Internal DC Supply Voltage for I/O Block DC Supply Voltage for Analog Core DC Supply Voltage for RTC DC Input Voltage Symbol VDDi VDDIO VDD VDDRTC VIN 1.2V VDD 3.3V VDD 3.3V VDD 3.0V VDD 3.3V Input buffer 3.3V Interface / 5V Tolerant input buffer DC Output Voltage Operating Temperature VOUT TOPR 3.3V Output buffer Commercial Rating Min 1.1 3.0 3.0 2.7 - 0.3 - 0.3 - 0.3 Max 1.3 3.6 3.6 3.6 VDDIO+0.3 5.25 VDDIO+0.3 0 to 70
o
Unit
V
C
25-1
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
ELECTRICAL DATA
S3C2440X RISC MICROPROCESSOR
D.C. ELECTRICAL CHARACTERISTICS
Table 25-3 and 25-4 define the DC electrical characteristics for the standard LVCMOS I/O buffers. Table 25-3. Normal I/O PAD DC Electrical Characteristics (VDD = 3.3V 0.3V, TA = 0 to 70 C) Symbol VIH VIL VT VT+ VTIIH IIL Parameters High level input voltage LVCMOS interface Low level input voltage LVCMOS interface Switching threshold Schmitt trigger, positive-going threshold Schmitt trigger, negative-going threshold High level input current Input buffer Low level input current Input buffer Input buffer with pull-up VOH High level output voltage Type B4 Type B6 Type B8 Type B10 Type B12 VOL Low level output voltage Type B4 Type B6 Type B8 Type B10 Type B12
NOTES: 1. Type B6 means 6mA output driver cell. 2. Type B8 means 8mA output driver cell. 3. Type B12 means 12mA output driver cells.
Condition
Min 2.0
Type
Max
Unit V
0.8 0.5VDD CMOS CMOS VIN = VDD VIN = VSS 0.8 -10 10 2.0
V V V V A A
-10 -60 -33
10 -10
IOH= - 4 mA IOH= - 6 mA IOH= - 8 mA IOH= -10 mA IOH = -12 mA IOL = 4 mA IOL = 6 mA IOL = 8 mA IOL = 10 mA IOL = 12 mA 0.4 V 2.4 V
25-2
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X RISC MICROPROCESSOR
ELECTRICAL DATA
Table 25-4. USB DC Electrical Characteristics Symbol VIH VIL IIH IIL VOH VOL Parameter High level input voltage Low level input voltage High level input current Low level input current Static Output High Static Output Low Vin = 3.3V Vin = 0.0V 15K 1.5K to GND to 3.6V -10 -10 2.8 Condition Min 2.5 0.8 10 10 3.6 0.3 Max Unit V V A A V V
Table 25-5. S3C2440X Power Supply Voltage and Current Parameter Typical VDDi / VDDIO Max. Operating frequency (FCLK) Max. Operating frequency (HCLK) Max. Operating frequency (PCLK) Typical normal mode power (Total VDDi + VDDIO) Typical normal mode power NOTE(3) (Total VDDi + VDDIO) Typical idle mode power NOTE(3) (Total VDDi + VDDIO) Typical slow mode power NOTE(3) (Total VDDi + VDDIO) Maximum Sleep mode power Typical Sleep mode power NOTE(3) Maximum RTC power Typical RTC power NOTE(3) 100 10 63 4 uA uA uA uA 97 mW 172 mW FCLK = 400MHz (F:H:P = 1:3:6) FCLK = 12MHz (F:H:P = 1:1:1) @1.2/3.3V, Room temperature All other I/O static. @3.0V, Room temperature X-tal = 32.768KHz for RTC 266 mW
NOTE(2) NOTE(3)
Value 1.2 / 3.3 400 133 67 369
Unit V MHz MHz MHz mW
Condition
NOTE(1)
NOTES: 1. I/D cache: ON, MMU: ON, Code on SRAM, FCLK:HCLK:PCLK = 400MHz:133MHz:66.7MHz :LCD ON (320x240x16bppx60Hz, color TFT):13KHz Timer internal mode(5 Channel run) :Audio(IIS&DMA,CDCLK=16.9MHz,LRCK=44.1KHz):Integer data quick sort(65536 EA) 2. Pocket PC 2003 MPEG play. 3. Room temperature specification.
25-3
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
ELECTRICAL DATA
S3C2440X RISC MICROPROCESSOR
Table 25-6. Typical Current Decrease by CLKCON Register (FCLK@400MHz) (Unit: mA) Peripherals NFC Current
NOTE: This table includes each power consumption of each peripherals. For example, If you do not use IIS and you turned off IIS block by CLKCON register, you can save the 0.5mA .
LCD
USBH
USBD
Timer
SDI
UART
RTC
ADC
IIC
IIS
SPI
Total
Figure 25-1. Typical Operating Voltage/Frequency Range (VDDIO=3.3V, @Room temperature & SMDK2440 board)
25-4
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X RISC MICROPROCESSOR
ELECTRICAL DATA
A.C. ELECTRICAL CHARACTERISTICS
tXTALCYC
1/2 VDD
1/2 VDD
NOTE:
The clock input from the XTIpll pin.
Figure 25-2. XTIpll Clock Timing
tEXTCYC tEXTHIGH tEXTLOW
1/2 VDD
VIH
VIH VIL VIL
VIH 1/2 VDD
NOTE:
The clock input from the EXTCLK pin.
Figure 25-3. EXTCLK Clock Input Timing
EXTCLK tEX2HC HCLK (internal)
Figure 25-4. EXTCLK/HCLK in case that EXTCLK is used without the PLL
25-5
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
ELECTRICAL DATA
S3C2440X RISC MICROPROCESSOR
HCLK (internal) tHC2CK CLKOUT (HCLK) tHC2SCLK SCLK
Figure 25-5. HCLK/CLKOUT/SCLK in case that EXTCLK is used
EXTCLK
nRESET
tRESW
Figure 25-6. Manual Reset Input Timing
25-6
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X RISC MICROPROCESSOR
ELECTRICAL DATA
Power PLL can operate after OM[3:2] is latched.
nRESET
XTIpll or EXTCLK
...
PLL is configured by S/W first time. tPLL VCO is adapted to new clock frequency.
Clock Disable
VCO output
... tRST2RUN ...
FCLK MCU operates by XTIpll or EXTCLK clcok. FCLK is new frequency.
Figure 25-7. Power-On Oscillation Setting Timing
25-7
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
ELECTRICAL DATA
S3C2440X RISC MICROPROCESSOR
EXTCLK
XTIpll
Clock Disable
tOSC2
VCO Output Several slow clocks (XTIpll or EXTCLK) FCLK
Power_OFF mode is initiated.
Figure 25-8. Sleep Mode Return Oscillation Setting Timing
25-8
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X RISC MICROPROCESSOR
ELECTRICAL DATA
tRCD
tRAD
tROD
tRDS
tRAD
tRDS
tRAD
tRDS
tRAD
tRDS
tRAD
tRDS
tRAD
tRDS
tRAD
tRDS
tRAD
tRCD
tROD
tRAD
Tacc
nGCSx
ADDR
'1'
tRDS
Figure 25-9. ROM/SRAM Burst READ Timing(I) (Tacs=0, Tcos=0, Tacc=2, Toch=0, Tcah=0, PMC=0, ST=0, DW=16bit)
nOE
DATA
HCLK
nBEx
tRDH
tRDH
tRDH
tRDH
tRDH
tRDH
tRDH
tRDH
25-9
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
ELECTRICAL DATA
S3C2440X RISC MICROPROCESSOR
tRCD
tRAD
tRBED
tROD
tRDS
tRAD
tRDS
tRAD
tRDS
tRAD
tRDS
tRAD
tRDS
tRAD
tRDS
tRAD
tRAD
tRDS
tRCD
tRAD
tROD
nGCSx
ADDR
Tacc
tRBED
tRDS
Figure 25-10. ROM/SRAM Burst READ Timing(II) (Tacs=0, Tcos=0, Tacc=2, Toch=0, Tcah=0, PMC=0, ST=1, DW=16bit)
25-10
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
nOE
DATA
HCLK
nBEx
tRDH
tRDH
tRDH
tRDH
tRDH
tRDH
tRDH
tRDH
2003.10.15
S3C2440X RISC MICROPROCESSOR
ELECTRICAL DATA
HCLK tHZD ADDR 'HZ' tHZD nGS 'HZ' tHZD nOE 'HZ' XnBREQ tXnBRQS tXnBRQH
tXnBACKD XnBACK
tXnBACKD
Figure 25-11. External Bus Request in ROM/SRAM Cycle (Tacs=0, Tcos=0, Tacc=8, Toch=0, Tcah=0, PMC=0, ST=0)
25-11
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
ELECTRICAL DATA
S3C2440X RISC MICROPROCESSOR
HCLK tRAD ADDR tRCD nGCSx Tacs tROD nOE tROD Tcah tRCD tRAD
Tcos Tacc Toch
nWBEx
'1'
tRDS DATA tRDH
Figure 25-12. ROM/SRAM READ Timing (I) (Tacs=2,Tcos=2, Tacc=4, Toch=2, Tcah=2, PMC=0, ST=0)
25-12
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X RISC MICROPROCESSOR
ELECTRICAL DATA
HCLK tRAD ADDR tRCD nGCSx Tacs tROD nOE tROD Tcah tRCD tRAD
Tcos Tacc tRBED Toch tRBED
nBEx
tRDS DATA tRDH
Figure 25-13. ROM/SRAM READ Timing (II) (Tacs=2, Tcos=2, Tacc=4, Toch=2, Tcah=2cycle, PMC=0, ST=1)
25-13
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
ELECTRICAL DATA
S3C2440X RISC MICROPROCESSOR
HCLK tRAD ADDR tRCD nGCSx Tacs Tcah tRWD nWE tRWD tRCD tRAD
Tcos Tacc tRWBED Toch tRWBED
nWBEx
Tcos Toch tRDD tRDD
DATA
Figure 25-14. ROM/SRAM WRITE Timing (I) (Tacs=2,Tcos=2,Tacc=4,Toch=2, Tcah=2, PMC=0, ST=0
25-14
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X RISC MICROPROCESSOR
ELECTRICAL DATA
HCLK tRAD ADDR tRCD nGCSx Tacs Tcah tRWD nWE tRWD tRCD tRAD
Tcos Tacc tRBED Toch tRBED
nBEx
tRDD DATA
tRDD
Figure 25-15. ROM/SRAM WRITE Timing (II) (Tacs=2, Tcos=2, Tacc=4, Toch=2, Tcah=2, PMC=0, ST=1)
25-15
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
ELECTRICAL DATA
S3C2440X RISC MICROPROCESSOR
HCLK tRC ADDR
nGCSx
Tacs Tacc = 6cycle Tacs sampling nWait delayed
nOE
nWait
DATA
NOTE:
The status of nWait is checked at (Tacc-1) cycle.
Figure 25-16. External nWAIT READ Timing (Tacs=0, Tcos=0, Tacc=6, Toch=0, Tcah=0, PMC=0, ST=0)
HCLK
ADDR
nGCSx
nWE
Tacc >= 2cycle
tWH tWS nWait
tRDD DATA tRDD
Figure 25-17. External nWAIT WRITE Timing (Tacs=0, Tcos=0, Tacc=4, Toch=0, Tcah=0, PMC=0, ST=0)
25-16
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X RISC MICROPROCESSOR
ELECTRICAL DATA
HCLK tRAD ADDR tRCD nGCSx Tacs tROD nOE tRAD
Tcos Tacc tRDS
DATA tRDH Figure 25-18. Masked-ROM Single READ Timing (Tacs=2, Tcos=2, Tacc=8, PMC=01/10/11)
HCLK tRAD ADDR tRCD nGCSx tRAD tRAD tRAD tRAD tRAD
tROD nOE Tacc Tpac tRDS DATA tRDH tRDH tRDH tRDH tRDH Tpac tRDS tRDS Tpac Tpac tRDS tRDS
Figure 25-19. Masked-ROM Consecutive READ Timing (Tacs=0, Tcos=0, Tacc=3, Tpac=2, PMC=01/10/11)
25-17
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
ELECTRICAL DATA
S3C2440X RISC MICROPROCESSOR
tSCSD
Trp
Trcd
tSBED
tSCD
'1'
tSAD
ADDR/BA
tSAD
A10/AP
tSRD
SCKE
nSRAS
nGCSx
nSCAS
tSWD
Tcl
tSDS
Figure 25-20. SDRAM Single Burst READ Timing (Trp=2, Trcd=2, Tcl=2, DW=16bit)
25-18
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
DATA
SCLK
nBEx
nWE
tSDH
2003.10.15
S3C2440X RISC MICROPROCESSOR
ELECTRICAL DATA
EXTCLK
tHZD 'HZ'
SCLK
tHZD
SCKE
'1'
tHZD
'HZ'
ADDR/BA tHZD
'HZ'
A10/AP tHZD
'HZ'
nGCSx tHZD
'HZ'
nSRAS tHZD
'HZ'
nSCAS tHZD 'HZ'
nBEx tHZD
'HZ'
nWE 'HZ' tXnBRQS XnBREQ tXnBRQL tXnBRQH
XnBACK tXnBACKD tXnBACKD
Figure 25-21. External Bus Request in SDRAM Timing (Trp=2, Trcd=2, Tcl=2)
25-19
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
ELECTRICAL DATA
S3C2440X RISC MICROPROCESSOR
SCLK
SCKE
'1' tSAD tSAD
ADDR/BA tSAD A10/AP tSCSD nGCSx tSCSD
tSRD nSRAS
tSRD
tSCD nSCAS
nBEx
'1' tSWD tSWD
nWE
DATA
'HZ'
Figure 25-22. SDRAM MRS Timing
25-20
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X RISC MICROPROCESSOR
ELECTRICAL DATA
SCLK
SCKE
'1' tSAD tSAD tSAD tSAD
ADDR/BA tSAD A10/AP tSCSD nGCSx tSCSD tSCSD tSAD
tSRD nSRAS Trp
tSRD
Trcd tSCD
nSCAS tSBED nBEx Tcl tSWD nWE
tSDS DATA tSDH
Figure 25-23. SDRAM Single READ Timing(I) (Trp=2, Trcd=2, Tcl=2)
25-21
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
ELECTRICAL DATA
S3C2440X RISC MICROPROCESSOR
SCLK
SCKE
'1' tSAD tSAD tSAD tSAD
ADDR/BA tSAD A10/AP tSCSD nGCSx tSCSD tSCSD tSAD
tSRD nSRAS Trp
tSRD
Trcd tSCD
nSCAS
tSBED nBEx Tcl tSWD nWE
tSDS DATA tSDH
Figure 25-24. SDRAM Single READ Timing(II) (Trp=2, Trcd=2, Tcl=3)
25-22
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X RISC MICROPROCESSOR
ELECTRICAL DATA
SCLK
SCKE
'1' tSAD tSAD
ADDR/BA tSAD A10/AP tSCSD nGCSx tSCSD
tSRD nSRAS Trp
tSRD '1' Trc tSCD
nSCAS
nBEx
'1' tSWD
nWE
DATA
'HZ' Before executing auto/self refresh command, all banks must be in idle state.
NOTE:
Figure 25-25. SDRAM Auto Refresh Timing (Trp=2, Trc=4)
25-23
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
ELECTRICAL DATA
S3C2440X RISC MICROPROCESSOR
Tcl
tSCSD
Trp
Trcd
tSBED
tSCD
'1'
tSAD
ADDR/BA
tSAD
A10/AP
tSRD
nSRAS
nSCAS
nGCSx
SCKE
tSWD
Tcl
Tcl
tSDS
Figure 25-26. SDRAM Page Hit-Miss READ Timing (Trp=2, Trcd=2, Tcl=2)
25-24
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
nWE
DATA
SCLK
nBEx
tSDH
2003.10.15
S3C2440X RISC MICROPROCESSOR
ELECTRICAL DATA
SCLK tCKED SCKE tSAD ADDR/BA tSAD A10/AP tSCSD nGCSx tSCSD '1' tSAD tCKED
tSRD nSRAS Trp
tSRD '1' tSCD '1' Trc
nSCAS
'1'
nBEx
'1' tSWD
'1'
nWE
'1'
DATA
'HZ'
'HZ'
NOTE:
Before executing auto/self refresh command, all banks must be in idle state.
Figure 25-27. SDRAM Self Refresh Timing (Trp=2, Trc=4)
25-25
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
ELECTRICAL DATA
S3C2440X RISC MICROPROCESSOR
SCLK
SCKE
'1' tSAD tSAD tSAD tSAD
ADDR/BA tSAD A10/AP tSCSD nGCSx tSCSD tSCSD tSAD
tSRD nSRAS Trp
tSRD
Trcd tSCD
nSCAS tSBED nBEx
tSWD nWE
tSDD DATA tSDD
Figure 25-28. SDRAM Single Write Timing (Trp=2, Trcd=2)
25-26
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X RISC MICROPROCESSOR
ELECTRICAL DATA
tSBED
tSCD
tSCSD
Trp
Trcd
'1'
tSAD
ADDR/BA
tSAD
A10/AP
tSRD
SCKE
nSRAS
nGCSx
nSCAS
tSWD
tSDD
Figure 25-29. SDRAM Page Hit-Miss Write Timing (Trp=2, Trcd=2, Tcl=2)
nWE
DATA
SCLK
nBEx
tSDD
25-27 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
ELECTRICAL DATA
S3C2440X RISC MICROPROCESSOR
XSCLK tXRS XnXDREQ tXAD XnXDACK Min. 3SCLK tCADL
Read Write
tXRS tCADH
Figure 25-30. External DMA Timing (Handshake, Single transfer)
Tf2hsetup VSYNC Tf2hhold HSYNC Tvfpd
VDEN
Tvspw
Tvbpd
HSYNC Tl2csetup VCLK Tvclkl VD Tvdsetup VDEN Tle2chold LEND Tlewidth Tve2hold Tvdhold Tvclkh Tvclk
Figure 25-31. TFT LCD Controller Timing
25-28
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X RISC MICROPROCESSOR
ELECTRICAL DATA
IISSCLK
tLRCK IISLRCK (out)
tSDO IISLRCK (out) tSDIS IISSDI (in) tSDIH
Figure 25-32. IIS Interface Timing
fSCL tSCLHIGH tSCLLOW
IICSCL
tSTOPH tBUF tSTARTS tSDAS tSDAH
IICSDA
Figure 25-33. IIC Interface Timing
25-29
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
ELECTRICAL DATA
S3C2440X RISC MICROPROCESSOR
SDCLK tSDCD
SDCMD (out)
tSDCS SDCMD (in)
tSDCH
tSDDD SDDATA[3:0] (out) tSDDS SDDATA[3:0] (in) tSDDH
Figure 25-34. SD/MMC Interface Timing
SPICLK tSPIMOD SPIMOSI (MO) tSPISIS SPIMOSI (SI) tSPISOD SPIMISO (SO) tSPIMIS SPIMISO (MI) tSPIMIH tSPISIH
Figure 25-35. SPI Interface Timing (CPHA=1, CPOL=1)
25-30
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X RISC MICROPROCESSOR
ELECTRICAL DATA
TACLS
TWRPH0
TWRPH1
TACLS
TWRPH0
TWRPH1
HCLK tCLED CLE tWED nFWE tWDS DATA[7:0] COMMAND tWDH tWED tCLED
HCLK tALED ALE tWED nFWE tWDS DATA[7:0] ADDRESS tWDH tWED tALED
Figure 25-36. NAND Flash Address/Command Timing
TWRPH0
TWRPH1
TWRPH0
TWRPH1
HCLK tWED tWED nFWE tWDS DATA[7:0] WDATA
HCLK tWED nFRE
tWED
tWDH DATA[7:0] RDATA
tRDS
tRDH
Figure 25-37. NAND Flash Timing
25-31
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
ELECTRICAL DATA
S3C2440X RISC MICROPROCESSOR
Table 25-7. Clock Timing Constants (VDDi, VDDalive, VDDiarm = 1.2 V 0.1 V, TA = 0 to 70 C, VDDMOP = 3.3V 0.3V) Parameter Crystal clock input frequency Crystal clock input cycle time External clock input frequency External clock input cycle time External clock input low level pulse width External clock to HCLK (without PLL) HCLK (internal) to CLKOUT HCLK (internal) to SCLK External clock input high level pulse width Reset assert time after clock stabilization PLL Lock Time Sleep mode return oscillation setting time The interval before CPU runs after nRESET is released. Symbol fXTAL tXTALCYC fEXT tEXTCYC tEXTLOW tEX2HC tHC2CK tHC2SCLK tEXTHIGH tRESW tPLL tOSC2 tRST2RUN Min 10 50 - 15.0 7 3 3 0 4 4 300 - - Typ - - - - - - - - - - - - 7 65536 - Max 20 100 66 - - 7 8 1 - - Unit MHz ns MHz ns ns ns ns ns ns XTIpll or EXTCLK uS XTIpll or EXTCLK XTIpll or EXTCLK
25-32
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X RISC MICROPROCESSOR
ELECTRICAL DATA
Table 25-8. ROM/SRAM Bus Timing Constants (VDDi, VDDalive, VDDiarm = 1.2 V 0.1 V, TA = 0 to 70 C, VDDMOP = 3.3V 0.3V) Parameter ROM/SRAM Address Delay ROM/SRAM Chip select Delay ROM/SRAM Output enable Delay ROM/SRAM read Data Setup time. ROM/SRAM read Data Hold time. ROM/SRAM Byte Enable Delay ROM/SRAM Write Byte Enable Delay ROM/SRAM output Data Delay ROM/SRAM external Wait Setup time ROM/SRAM external Wait Hold time ROM/SRAM Write enable Delay Symbol tRAD tRCD tROD tRDS tRDH tRBED tRWBED tRDD tWS tWH tRWD Min 3 2 2 1 0 2 2 2 1 0 3 Typ - - - - - - - - - - - Max 7 7 5 3 1 6 6 7 3 1 6 Unit ns ns ns ns ns ns ns ns ns ns ns
Table 25-9. Memory Interface Timing Constants (3.3V) (VDDi, VDDalive, VDDiarm = 1.2 V 0.1 V, TA = 0 to 70 C, VDDMOP = 3.3V 0.3V) Parameter SDRAM Address Delay SDRAM Chip Select Delay SDRAM Row active Delay SDRAM Column active Delay SDRAM Byte Enable Delay SDRAM Write enable Delay SDRAM read Data Setup time SDRAM read Data Hold time SDRAM output Data Delay SDRAM Clock Enable Delay Symbol tSAD tSCSD tSRD tSCD tSBED tSWD tSDS tSDH tSDD Tcked Min 2 2 2 2 2 2 1 0 2 2 Typ - - - - - - - - - - Max 7 5 5 5 6 6 3 1 8 5 Unit ns ns ns ns ns ns ns ns ns ns
25-33
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
ELECTRICAL DATA
S3C2440X RISC MICROPROCESSOR
Table 25-10. External Bus Request Timing Constants (VDD = 1.2 V 0.1 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter eXternal Bus Request Setup time eXternal Bus Request Hold time eXternal Bus Ack Delay HZ Delay Symbol tXnBRQS tXnBRQH tXnBACKD tHZD Min 2 0 4 3 Typ. - - - - Max 4 1 10 8 Unit ns ns ns ns
Table 25-11. DMA Controller Module Signal Timing Constants (VDD = 1.2 V 0.1 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter eXternal Request Setup aCcess to Ack Delay when Low transition aCcess to Ack Delay when High transition eXternal Request Delay Symbol tXRS tCADL tCADH tXAD Min 2 4 4 2 Typ. - - - - Max 4 9 9 - Unit ns ns ns SCLK
25-34
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X RISC MICROPROCESSOR
ELECTRICAL DATA
Table 25-12. TFT LCD Controller Module Signal Timing Constants (VDD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter Vertical sync pulse width Vertical back porch delay Vertical front porch dealy VCLK pulse width VCLK pulse width high VCLK pulse width low Hsync setup to VCLK falling edge VDEN set up to VCLK falling edge VDEN hold from VCLK falling edge VD setup to VCLK falling edge VD hold from VCLK falling edge VSYNC setup to HSYNC falling edge VSYNC hold from HSYNC falling edge
NOTES: 1. HSYNC period 2. VCLK period
Symbol Tvspw Tvbpd Tvfpd Tvclk Tvclkh Tvclkl Tl2csetup Tde2csetup Tde2chold Tvd2csetup Tvd2chold Tf2hsetup Tf2hhold
Min VSPW + 1 VBPD+1 VFPD+1 1 0.5 0.5 0.5 0.5 0.5 0.5 0.5 HSPW + 1 HBPD + HFPD + HOZVAL + 3
Typ - - - - - - - - - - - - -
Max - - - - - - - - - - - - -
Units Phclk (note1) Phclk Phclk Pvclk (note2) Pvclk Pvclk Pvclk Pvclk Pvclk Pvclk Pvclk Pvclk Pvclk
Table 25-13. IIS Controller Module Signal Timing Constants (VDD = 1.2 V 0.1 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter IISLRCK delay time IISDO delay time IISDI Input Setup time IISDI Input Hold time CODEC clock frequency Symbol tLRCK tSDO tSDIS tSDIH fCODEC Min 0 0 5 0 1/16 Typ. - - - - - Max 3 2 10 1 1 Unit ns ns ns ns fIIS_BLOCK
25-35
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
ELECTRICAL DATA
S3C2440X RISC MICROPROCESSOR
Table 25-14. IIC BUS Controller Module Signal Timing (VDD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter SCL clock frequency SCL high level pulse width SCL low level pulse width Bus free time between STOP and START START hold time SDA hold time SDA setup time STOP setup time Symbol fSCL tSCLHIGH tSCLLOW tBUF tSTARTS tSDAH tSDAS tSTOPH Min - std. 4.0 fast 0.6 std. 4.7 fast 1.3 std. 4.7 fast 1.3 std. 4.0 fast 0.6 std. 0 fast 0 std. 250 fast 100 std. 4.0 fast 0.6 Typ. - - - - - - - - Max std. 100 fast 400 - - - - std. - fast 0.9 - - Unit kHz s s s s s ns s
NOTES: Std. means Standard Mode and fast means Fast Mode. 1. The IIC data hold time(tSDAH) is minimum 0ns. (IIC data hold time is minimum 0ns for standard/fast bus mode in IIC specification v2.1.) Please check the data hold time of your IIC device if it's 0 nS or not. 2. The IIC controller supports only IIC bus device(standard/fast bus mode), not C bus device.
Table 25-15. SD/MMC Interface Transmit/Receive Timing Constants (VDD = 1.2 V 0.1 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter SD Command output Delay time SD Command input Setup time SD Command input Hold time SD Data output Delay time SD Data input Setup time SD Data input Hold time Symbol tSDCD tSDCS tSDCH tSDDD tSDDS tSDDH Min 0 5 0 0 5 0 Typ. - - - - - - Max 1 11 1 1 11 1 Unit ns ns ns ns ns ns
25-36
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X RISC MICROPROCESSOR
ELECTRICAL DATA
Table 25-16. SPI Interface Transmit/Receive Timing Constants (VDD = 1.2 V 0.1 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter SPI MOSI Master Output Delay time SPI MOSI Slave Input Setup time SPI MOSI Slave Input Hold time SPI MISO Slave output Delay time SPI MISO Master Input Setup time SPI MISO Master Input Hold time Symbol tSPIMOD tSPISIS tSPISIH tSPISOD tSPIMIS tSPIMIH Min 0 0 0 6 5 0 Typ. - - - - - - Max 1 1 1 18 15 1 Unit ns ns ns ns ns ns
Table 25-17. USB Electrical Specifications (VDD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter Supply Current Suspend Device Leakage Current Hi-Z state Input Leakage Input Levels Differential Input Sensitivity Differential Common Mode Range Single Ended Receiver Threshold Output Levels Static Output Low Static Output High Capacitance Transceiver Capacitance CIN Pin to GND 20 pF VOL VOH RL of 1.5Kohm to 3.6V RL of 15Kohm to GND 2.8 0.2 3.6 V VDI VCM VSE | (D+) - (D-) | Includes VDI range 0.2 V 0.8 0.8 2.5 2.0 ILO 0V < VIN < 3.3V -10 10 A ICCS 10 A Symbol Condition Min Max Unit
25-37
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
ELECTRICAL DATA
S3C2440X RISC MICROPROCESSOR
Table 25-18. USB Full Speed Output Buffer Electrical Characteristics (VDD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter Driver Characteristics Transition Time Rise Time Fall Time Rise/Fall Time Matching Output Signal Crossover Voltage Drive Output Resistance TR TF Trfm Vcrs Zdrv Steady state drive CL = 50pF CL = 50pF (TR / TF ) 4.0 4.0 90 1.3 28 20 20 111.1 2.0 44 % V ohm ns Symbol Condition Min Max Unit
Table 25-19. USB Low Speed Output Buffer Electrical Characteristics (VDD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter Rising Time Symbol Condition Driver Characteristics TR TF Trfm Vcrs CL = 50pF CL = 350pF CL = 50pF CL = 350pF (Tr / Tf ) 80 1.3 75 300 125 2.0 % V 75 300 ns Min Max Unit
Falling Time Rise/Fall Time Matching Output Signal Crossover Voltage
Note: All measurement conditions are in accordance with the Universal Serial Bus Specification 1.1 Final Draft Revision.
25-38
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440X RISC MICROPROCESSOR
ELECTRICAL DATA
Table 25-20. NAND Flash Interface Timing Constants (VDDi, VDDalive, VDDiarm = 1.8 V 0.15 V, TA = 0 to 70 C, VDDIO = 3.3V 0.3V) Parameter NFCON Chip Enable delay NFCON CLE delay NFCON ALE delay NFCON Write Enable delay NFCON Read Enable delay NFCON Write Data Setup time NFCON Write Data Hold time NFCON Read Data Setup requirement time NFCON Read Data Hold requirement time Symbol tCED tCLED tALED tWED tRED tWDS tWDH tRDS tRDH Min - - - - - - 3.7 3 0.3 Max 5.3 5.7 5.5 5.6 5.9 5.4 5.5 - - Unit ns ns ns ns ns ns ns ns ns
25-39
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.10.15
ELECTRICAL DATA
S3C2440X RISC MICROPROCESSOR
NOTES
25-40
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
S3C2440X RISC MICROPROCESSOR
MECHANICAL DATA
MECHANICAL DATA
PACKAGE DIMENSIONS
0.15 C x 2 14.00 B A
SAMSUNG
14.00
289-FBGA-1414
0.15 C x 2 0.35 ?0.05
0.10 C
0.45
1.22
?0.05
0.12 MAX C TOLERANCE
?0.10
Figure 26-1. 289-FBGA-1414 Package Dimension 1 (Top View)
26-1
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.
2003.09.25
MECHANICAL DATA
S3C2440X RISC MICROPROCESSOR
14.00
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U
A1 INDEX MARK
0.80 x 16 = 12.80
0.05
0.80
0.80
289 -
0.45
0.05
0.15 M C A 0.08 M C
14.00 B
TOLERANCE
0.10
Figure 26-2. 289-FBGA-1414 Package Dimension 2 (Bottom View) The recommended land open size is 0.39 - 0.41mm diameter.
26-2
Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.

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